Lalit Joshi — Software Engineer
• 4 years of experience in IP & SoC Verification. • Verification using System Verilog and UVM. • Developing comprehensive test plan and reusable test content in SV and grits. • Implementing testbench and reusable checkers. Skill set • HDL/HVL: Verilog, System Verilog. • Verification Methodology: UVM. • Protocols: AXI, APB, MESI, SPI, I2C • Scripting languages: Python, Perl, C, C++. • Tools: Synopsys VCS, Zebu Emulator • Operating system: Linux. • Debugging tool: Synopsis Verdi.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SoC design and verification methodologies.
Location: Nainital, Uttarakhand, India
Experience: 5 yrs 4 mos
Skills
- System Verilog
- Uvm
Career Highlights
- 4 years of experience in IP & SoC Verification.
- Expert in System Verilog and UVM methodologies.
- Strong background in developing test plans and reusable content.
Work Experience
AMD
Senior Silicon Design Engineer (1 yr 4 mos)
Intel Corporation
SoC Design Engineer (2 yrs 6 mos)
Indian Institute of Technology, Roorkee
Teaching Assistant (9 mos)
Placement and Internship Cell, IIT Roorkee
Placement Coordinator (1 yr 3 mos)
Gradeup (Gradestack Learning Pvt Ltd)
Associate (GATE Academics Division) (3 mos)
Education
Master of Technology - MTech at Indian Institute of Technology, Roorkee
Bachelor of Technology - BTech at Bipin Tripathi Kumaon Institute Of Technology
HSC at Aryaman Vikram Birla Institute of Learning, Haldwani
SSC at Aryaman Vikram Birla Institute of Learning, Haldwani
