RHINY JACOB — Software Engineer
Experienced ASIC verification engineer (7 plus years)with a demonstrated history of working in RTL design verification Skilled in Universal Verification Methodology (UVM), SystemVerilog,AMBA protocols and Application-Specific Integrated Circuits (ASIC). Strong engineering professional with a Master of Technology - MTech focused in VLSI and Embedded Systems from Rajagiri School of Engineering and Technology, Rajagiri Valley P.O, Kakkanad, Kochi- 682 039.
Stackforce AI infers this person is a Telecommunications ASIC Verification Engineer with extensive experience in VLSI design.
Location: Ernakulam, Kerala, India
Experience: 7 yrs 1 mo
Skills
- Very-large-scale Integration (vlsi)
- Application-specific Integrated Circuits (asic)
- Universal Verification Methodology (uvm)
Career Highlights
- 7+ years of ASIC verification experience.
- Expert in UVM and SystemVerilog methodologies.
- Strong academic background in VLSI and Embedded Systems.
Work Experience
Intel Corporation
Design Verification Engineer (4 yrs 7 mos)
Qualcomm
Design Verification EngineerII (2 yrs 10 mos)
Mbit wireless pvt limited
ASIC verification Engineer (1 yr 5 mos)
RSET Kakkanad
Worked as Teaching Assistant (3 mos)
Worked as Graduate Assistant (10 mos)
Education
Master of Technology - MTech at Rajagiri School of Engineering and Technology, Rajagiri Valley P.O, Kakkanad, Kochi- 682 039
Bachelor of Technology - BTech at Toc-H Institute of Science and Technology, Arakunnam
