Mallikarjun Devaramani

CEO

Bengaluru, Karnataka, India25 yrs 6 mos experience

Key Highlights

Expert in managing multiple SoC projects simultaneously.
Proven track record in physical design and low-power design.
Strong leadership in project and program management.

Stackforce AI infers this person is a Semiconductor expert with extensive experience in physical design and project management.

Contact

Skills

Core Skills

Physical DesignProject/program Management

Other Skills

Managing Multiple SoC Projects in parallelPower Integrity ClosureLow-power DesignStatic Timing AnalysisSoC RTL2GDSII and Foundry relationshipPost-Silicon supportFIBSoC RTL2GDSIIVLSIFloorplanningPower Gating DesignsIR-DropEM-AnalysisSI/Noise-AnalysisHierarchical Floorplanning

Experience

25 yrs 6 mos

Total Experience

2 yrs 8 mos

Average Tenure

11 mos

Current Experience

Tessolve

AVP-Physical Design @Tessolve

Jun 2025 – Present · 11 mos · Bengaluru, Karnataka, India · On-site

Managing Multiple SoC Projects in parallelPhysical DesignPower Integrity ClosureLow-power DesignStatic Timing AnalysisProject/Program Management

Quest global

Director - Physical Design Delivery Head

Mar 2024 – May 2025 · 1 yr 2 mos · Bengaluru, Karnataka, India

SoC RTL2GDSII and Foundry relationshipPost-Silicon supportFIBManaging Multiple SoC Projects in parallelPhysical DesignProject/Program Management+2

Samsung semiconductor

Associate Technical Director - Physical Design

Oct 2021 – Feb 2024 · 2 yrs 4 mos · Bengaluru, Karnataka, India

Projects Managed – True RTL2GDS + SoC TO’s
Domain Skills- Expert in SoC Physical Design Including Partition Hier-Flr, PnR, STA, IR, PV, FV/LEC/VCLP & LDRC. Understand RTL/DFT/DV/Custom-Design.
44+ TO’s. Managed 2-3 Tapeouts every month and 1-SoC Tapeout.
Managed Two (SoC + Testchip) main stream teams at same time.
Customer project to support Foundry business
Screening INPUT- Netlist/SDC(CN) + Design related documents
Partition Floorplan- IO/BUMP Plan, Macro/SRAM placement, Partition commit with best optimization for Area/Pins/Partition shapes/Channel/Power Domains for Low power
TOP+HM(Blocks)- Flr, PlaceOpt, CTS, Ropute-Opt, Chip-Finish and ECO cycle for STA/IR/PV – Conduct review @each stage
PD- Flr, IO/Bump planning, Place, CTS, Route-Opt
Sign-Off (FV/LEC/CLP, LDRC, STA, IR, PV) – Conduct reviews time to time and qualify
Tapeout Checklist + Reviews – conduct + Close Tapeout with Process team
Worked on PPAS (Power Performance Area Schedule) priorities
Team R&R Managed-
RTL- RTL Integration and modeling, SDC(CN), Synthesis + Review + Data handoff hand-off with checklist
DFT- SCAN, MBIST high performance 3.9GHz. RTL/Syn-NTL & SDF sims + Vector generation for playback sims +Review+ Vector handoff hand-off with checklist.
DV- RTL, Netlist Zero/Unit delay sims, SDF-GLS + Vector generation for IR and Si-Test
PD- Flr, IO/Bump planning, Place, CTS, Route-Opt
Sign-Off (FV/LEC/CLP, LDRC, STA, IR, PV) – Conduct reviews time to time and qualify
Tapeout Checklist + Reviews – conduct + Test-Spec Doc release to test team

SoC RTL2GDSII and Foundry relationshipPost-Silicon supportFIBManaging Multiple SoC Projects in parallelPhysical DesignPower Integrity Closure+3

Guc

Senior Technical Manager

Sep 2018 – Sep 2021 · 3 yrs · Hsinchu City, Taiwan, Taiwan

Mediatek

2 roles

Dept Manager

Apr 2015 – Sep 2018 · 3 yrs 5 mos

Sr, Tech Manager

Aug 2014 – Mar 2015 · 7 mos

Open-silicon, inc.

Design Manager

Oct 2012 – Jul 2014 · 1 yr 9 mos · Bangalore

Amd

MTS - ASIC

Feb 2011 – Oct 2012 · 1 yr 8 mos · Bangalore

Cypress semiconductor

Sr, Staff Design Engineer

Apr 2004 – Jan 2011 · 6 yrs 9 mos

Cadence design systems (i) pvt ltd

Application Engineer

May 2001 – Apr 2004 · 2 yrs 11 mos

Worked with Global/MNC Cadence customers and SCL Fab, Bench Marks. Design Evaluations and Customers 0.25u, 0.18u, 0.13u Real Time Projects. Developed SE (Silicon Ensemble) Tutorial Kit for Customers. Delivered Synthesis, P&R (SoC-Encounter, Silicon Ensemble) and PKS Trainings.