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Amarnath Kulal

Software Engineer

Bengaluru, Karnataka, India6 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in DFT and Scan Insertion for ASICs.
  • Proven experience in post-silicon debug and yield issues.
  • Strong background in emulation and FPGA solutions.
Stackforce AI infers this person is a DFT and ASIC specialist with a focus on post-silicon validation.

Contact

LinkedIn

Skills

Core Skills

DftScan Insertion

Other Skills

DFT CompilerDFTC Issues in Design CompilerAutomatic Test Pattern Generation (ATPG)Scan CompressionSystem on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)Coverage AnalysisSimulation DebugNo Timing SimulationTiming SimulationVeloceTechnical PresentationsEmulationStatic Timing AnalysisCalibre

About

DFT Engineer with knowledge of Scan Insertion , Scan STA , Scan RTL generation Working on upcoming MediaTek ASICs/SOCs for complete ATPG Cycle ,Scan Insertion ,Silicon Bring-up, Yield issues and Post silicon debug Previously worked as an Application Engineer for focused defense and private market for Emulation ,DFT, FPGA and DO-254 solutions.

Experience

6 yrs 11 mos
Total Experience
3 yrs 5 mos
Average Tenure
5 yrs 1 mo
Current Experience

Mediatek

2 roles

Staff Engineer

Promoted

May 2024 – Present · 1 yr 11 mos · Greater Bengaluru Area

DFT Engineer

Mar 2021 – May 2024 · 3 yrs 2 mos · Greater Bengaluru Area

  • DFT Engineer at Mediatek
Scan InsertionDFT CompilerDFT

Trident techlabs pvt. ltd.

Application Engineer ( DFT , Emulation )

Jan 2019 – Nov 2020 · 1 yr 10 mos · India

Education

BNM Institute Of Technology

Bachelor of Engineering — Electronics and Communications Engineering

Aug 2014 – Jul 2018

Vasavadatta Vidya Vihar

Jan 2000 – Jan 2012

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