Anurag Kinger — Software Engineer

🔧 Physical Design Engineer | Advanced Node SoC Implementation | RTL-to-GDSII | Clocking Architectures | EDA Innovator I’m a seasoned Physical Design Engineer at Qualcomm Semiconductor, with a strong track record of delivering high-performance SoCs across cutting-edge technology nodes including 3nm, 4nm, 7nm, 10nm, and 16nm. My expertise spans the full RTL-to-GDSII flow, with a focus on Place & Route, timing closure, signal integrity, and physical verification. With a deep technical foundation and a passion for innovation, I lead cross-functional teams to solve complex design challenges in advanced nodes. I specialize in: Full-chip physical design and integration MMMC timing closure and physical synthesis Noise analysis, DFM routing, and crosstalk mitigation DRC, LVS, ERC, CLP, and FV verification Complex clocking structures and CTS optimization Tcl scripting and flow automation As a technical leader, I drive execution excellence, mentor engineers, and collaborate across architecture, RTL, and verification teams to ensure first-time-right silicon. My current interests lie in researching novel placement and routing techniques, and exploring machine learning applications in EDA. Let’s connect if you’re passionate about pushing the boundaries of semiconductor design or exploring innovations in physical implementation!

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and EDA.

Location: Noida, Uttar Pradesh, India

Experience: 12 yrs 7 mos