Nov 2022 – Mar 2025 · 2 yrs 4 mos · Noida, Uttar Pradesh, India

• CPU Synthesis & Implementation Engineer | Digital Design | Power & Performance Optimization | Tapeout
• Silicon Tapeout Contributions: Played a key role in the synthesis and implementation of 8+ chips (and counting) across diverse applications, including mobile, compute, automotive, and wearables.
• Power & Performance Optimization: Conducted Synthesis PPA trials focused on dynamic power optimization for high-performance CPU cores, improving efficiency without compromising performance.
• End-to-End Ownership: Managed full-flat CPU subsystem synthesis, including Clock Management System (CMS), Clock Domain Crossing (CDC) based Skew checks, ensuring design integrity and timing closure.

Jul 2020 – Nov 2022 · 2 yrs 4 mos · Noida, Uttar Pradesh, India

• Digital Design | CPU Subsystem | Synthesis | Low Power | Formal Verification
• Synthesis & Constraints Management: Led synthesis efforts for multiple CPU subsystems (CPUSS MHM), gaining deep expertise in managing flat-level constraints to optimize design performance and timing closure.
• Logic Equivalence & Low Power Verification: Performed full-flat logic equivalence checks (LEC) and low power verification to ensure design integrity, functionality, and power efficiency.
• Multi-Project Execution: Successfully delivered multiple projects within tight deadlines while maintaining high-quality standards.
• Mentorship & Training: Actively mentored new hires, conducted training sessions, and facilitated smooth onboarding to accelerate team productivity.

Jan 2020 – Jun 2020 · 5 mos · Noida, Uttar Pradesh, India

• CPU Synthesis Intern | Qualcomm Noida Design Centre
• Hands-on Synthesis Experience: Completed a 6-month internship as part of the CPU Synthesis team, gaining foundational knowledge of the end-to-end synthesis flow.
• Independent Module Ownership: Successfully owned and executed the complete synthesis of an MHM, ensuring formal handoffs and meeting design requirements.
• Verification & Signoff Support: Contributed to formal/logic verification and low power signoff checks for a flat CPU subsystem, enhancing design integrity and efficiency.

Apr 2019 – Jul 2020 · 1 yr 3 mos · New Delhi, Delhi, India · On-site

• Scheduled and coordinated the placement process in collaboration with the University Relations team.
• Invigilated tests and examinations conducted during the process.
• Managed end-to-end on-campus placement drives for multiple companies, ensuring a seamless hiring experience.

Aug 2018 – Jun 2020 · 1 yr 10 mos · New Delhi, Delhi, India · On-site

• Assisted in practical laboratory sessions for bachelor’s students, ensuring a hands-on learning experience.
• Evaluated assignments and provided constructive feedback to support student learning.

Jan 2017 – May 2018 · 1 yr 4 mos · Noida Area, India · On-site

• Research & Analytics | Semiconductor | Electronics | IoT | Machine Learning
• As a part of the Research team, leveraged analytical skills and technical expertise to assess various aspects of inventions, analyze them, and determine the appropriate course of action based on project requirements.
• Successfully executed four major and critical invalidation projects in the semiconductor domain, which received high client appreciation and were recognized as some of the finest industry deliverables at the time.
• Worked on office actions that contributed to the granting of two patents for Detroit Electric.