Shantanu Jaidwal — Software Engineer
Having sound knowledge on various aspects of backend VLSI/ASIC Physical Design flow from Synthesis to GDS ( Floor planning, Placement, CTS, Routing, Timing Closure ,ECO implementation ) and on Physical Implementation tools such as Fusion Compiler and STA Primetime. Ability to work in an environment which challenges an individual's ability and skills to meet deadlines.
Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in backend design and timing analysis.
Location: Gurugram, Haryana, India
Experience: 3 yrs 10 mos
Skills
- Physical Design
- Low-voltage Design
Career Highlights
- Expert in backend VLSI/ASIC Physical Design flow.
- Proficient in tools like Fusion Compiler and STA Primetime.
- Strong problem-solving and communication skills.
Work Experience
Intel Corporation
Physical Design Engineer (3 yrs 10 mos)
Graduate Intern (11 mos)
Education
Master of Technology - MTech at Thapar Institute of Engineering & Technology
Bachelor of Technology at SRM IST Chennai
