Khushbu Kosalkar — Software Engineer

Experience with the EDA tools: 1) Synopsys VCS, DC, ICC, ICC2 and PrimeTime(PT) used for Physical Design. 2)Cadence virtuoso used for designing the basic amplifiers ( CS,CD,CG stage ), cascode amplifiers ( Telescopic and Folded stage) and OP-AMP design ( basic two stage and telescopic stage). ▪Projects done in the field of: -> Digital Circuit Design and Verilog ->System verilog Projects : 1.Optimization of Constant Matrix Multiplication using Ternary Carry Save Adder with low power, minimal area and High Throughput. (August2020-November 2020) 2.Insertion and Prevention of Hardware Trojan at Various Stages of IC Design. (August 2020-November 2020) 3.Design of low-power flipflop using clock-gating. (February 2021-June 2021) 4.Design and analysis of 8 –bit processor using system Verilog. 5.Power loss detector using IOT. ▪Area of Interest : ->Digital Circuit Design, Verification,RTL Design and Physical Design. Protocols: UART,SPI,I2C Experienced on Cadence Protium X1,X2 and Palladium Z2 tools that used for prototyping .Worked on Validating design using the cadence tool. Experienced on Evaluating the new features that will ease the user’s life.

Stackforce AI infers this person is a Digital Circuit Design Engineer with expertise in EDA tools and low-power design.

Location: Gondia, Maharashtra, India

Experience: 3 yrs