Suhas reddy

Software Engineer

Bengaluru, Karnataka, India16 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Functional Verification and System Verilog.
  • Hands-on experience with AMBA protocols and UVM.
  • Proficient in debugging and verifying complex modules.
Stackforce AI infers this person is a Verification Engineer in the Semiconductor industry.

Contact

Skills

Core Skills

Functional VerificationSystem VerilogAmba Axi4-liteUvm

Other Skills

DebuggingVerilogCEmbedded SystemsSpecmanEDAOpen Verification MethodologyModelSimAMBA AHBDigital ElectronicsASICSPICEAssertionsXilinx ISESoC

About

Having a very good exposure verifying IP's related to Trace & debug module such as PTM/ETM, JTAG and also hands on DDR at SoC Level. Also worked on Gate level simulations (GLS) for timing checks in all 3 cases of min, max and typical cases. Also verg good knowledge on the AMBA protocols such as APB,AXI4-LITE and AHB in understanding and also verifying it from building the environment to coverage closure using System verilog as well as using the Universal Verification Methodology (UVM). Application engineer for Nextop's BUGSCOPE (Creating automatic assertions and coverage goals) and TREK (Creating graphical representation of the design under testing).

Experience

16 yrs 3 mos
Total Experience
5 yrs 1 mo
Average Tenure
14 yrs 5 mos
Current Experience

Intel corporation

Senior Verification Engineer

Mar 2018Present · 8 yrs 1 mo · Bengaluru Area, India

Functional VerificationSystem VerilogUVMDebugging

St ericsson

ASIC Verification engineer

Nov 2011Present · 14 yrs 5 mos · Bangalore

Cvc pvt ltd

ASIC Verification Engineer

Jul 2011Nov 2011 · 4 mos · Bangalore

  • Had done my internship project at CVC Pvt Ltd on understanding and verifying AMBA AXI4-Lite protocol using SV and UVM and also had worked on other AMBA protocols for verifying the same. I was also working as an application engineer(AE) for few automatic assertion and coverage generator tools.
AMBA AXI4-LiteSystem VerilogUVM

Sicon design technologies pvt. ltd.

Asic Verification Engineer

Jan 2011Jan 2012 · 1 yr

Cvc

student

Jan 2009Jan 2010 · 1 yr

  • Had done a course on Verification using System Verilog.

Mcis, inc.

Student

Jan 2009Jan 2010 · 1 yr

  • MS in VLSI - CAD

Education

Manipal Institute of Technology

MS — Electronics And Communication

Jan 2009Jan 2011

Visvesvaraya Technological University

BE — Electronics And Communication

Jan 2005Jan 2009

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