Veerendra Jonna — Software Engineer

• Intel Client/Mobility Boot/Reset/Power Management Architecture and Design • Intel Server Micro-Architect • Graphics DRAM PHY Digital Design • Wireless Modem Architecture and Design Integration • Wireless Modem System Control and Power Management Architecture and Design • OVM Base Classes and Constrained Random Verification Environment • Static Timing Analysis and Clock Tree Synthesis • UPF & Power Aware Concepts • ARM RISC SW/HW Architecture: Compiler, Linker, Instruction set, MMU • DSP SW/HW Architecture: Assembler, Instruction set, Pipelining • Network Reference Models in “Perl” • System Level verification of VDSL2 CO and CPE • HDLC/EFM Packet Encoders and Decoders • Network Packet Buffer Management control Specialties: • IP/Module/Top Level Modem Design • Top Level Modem Clocking/Resetting/Power Management Design • BBIC DigRFv4 Adaptation Design/Verification • System/Subsystem/Module level verification environment Verilog/SV(OVM based) • OVM Top Level verification environment • STA/UPF/CTS constraints/analysis • Netlist/GLS sim setup/bringup/debug • RISC/DSP Processor architectures • Network reference models and verification env setup • Signal processing reference models and verification env setup

Stackforce AI infers this person is a highly skilled engineer in VLSI and SoC design, specializing in power management and digital design.

Location: Bengaluru, Karnataka, India

Experience: 22 yrs 3 mos