P

Prashant K.

Software Engineer

India9 yrs experience

Key Highlights

  • Expert in SystemVerilog and UVM for RTL verification.
  • Proficient in formal verification using Jasper Gold.
  • Strong analytical skills in coverage metrics.
Stackforce AI infers this person is a Verification Engineer specializing in RTL and formal verification within the semiconductor industry.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogFormal Verification

Other Skills

UVMSVArtl verificationcoverage metricsJasper GoldFPVUNRVerilogData StructuresPerlCC++MatlabLinuxPython

About

Hello, I have experience in following:- ๐Ÿ‘‰๐Ÿฟ Creating Systemverilog /UVM/SVA based rtl verification environment, maintain those, in accordance with the flow of Verification ๐Ÿ‘‰๐Ÿฟ Formal verification(basics) using formal tools such jasper gold for FPV | UNR. ๐Ÿ‘‰๐Ÿฟ Analyzing coverage metrics. ๐Ÿ‘‰๐Ÿฟ Familiar with Tools vcs | irun | imc | simvision | jasper gold | ncverilog | emanager etc.

Experience

9 yrs
Total Experience
2 yrs 7 mos
Average Tenure
1 yr 1 mo
Current Experience

Intel corporation

Sr. SoC Verification Engineer

Mar 2025 โ€“ Present ยท 1 yr 1 mo ยท Penang, Malaysia ยท Hybrid

SystemVerilogUVMSVArtl verificationcoverage metricsUniversal Verification Methodology (UVM)

Nxp semiconductors

Verification Engineer

Jan 2023 โ€“ Feb 2025 ยท 2 yrs 1 mo ยท Bengaluru, Karnataka, India ยท On-site

Formal verificationJasper GoldFPVUNRFormal Verification

Intel corporation

Senior Design Verification Engineer

Jun 2020 โ€“ Jun 2022 ยท 2 yrs ยท Bengaluru, Karnataka, India

Nxp semiconductors

2 roles

Senior Design Verification Engineer

Promoted

May 2019 โ€“ May 2020 ยท 1 yr

Design Verification Engineer

Jun 2016 โ€“ Apr 2019 ยท 2 yrs 10 mos

Education

Motilal Nehru National Institute Of Technology

Bachelor of Technology (B.Tech.) โ€” Electronics and Communication Engineering

Jan 2012 โ€“ Jan 2016

Patna Muslim High School

Class XII โ€” Science

Jan 2010 โ€“ Jan 2011

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