Pranav Joshi — Director of Engineering

Currently working as Director Engineer at eInfochips Ltd. since Feb 2022. Prior that was working as Delivery Manager at eInfochips Ltd. from May 2021 till Feb 2022. Project Lead at eInfochips Limited, a leading Product Service Company in the field of ASIC design & Verification and Embedded Systems, Software since Dec-2000 till Jun 2010. Also worked as Sr. Member Tech. Staff at SiBridge Technology Ltd from Jun 2010-May2012. # Expertise in HVL like Specman-e Language, System Verilog. # Hands on experience in C++ and SystemC. # Hands on experience in Scripting: Shell, Perl, Python # Experience in Verification Methodology: eRM, OVM, UVM and VMM. # Experience of developing Verification IP (VIP): CXL2.0, PCI-ExpressGen1, 2,3,4,5, USB2.0/3.0 802.3 Ethernet, SPI4.2, Fibre-Channel, MIPI-RFFE, MIPI-SlimBus, FlexRay, CAN, MHL and Customized Protocol. # Rich experience in creation of architecture of VIPs and Verification Environment (VE) using System Verilog and e Language. # Successfully Managed ODC Projects for SoC Verification (Networking, Storage, Test and Measurement, Emulation domain), that includes Scope Definition, Planning-Tracking, Testbench and Testplan Development and Execution. # Successfully Managing OVC development program at Offshore. # Well converge with Project Management Tools and report generation. Specialties: 1. Rich experience in e and SV in UVM, eRM, OVM and VMM. 2. VIP product development skill and Support management. 3. Effective handling of large size team and multiple projects at a time. [100+ Engineers] 4. As a part of Service Industry worked with almost 20 Different well-known customers for Project Execution and Product Development+Support.

Stackforce AI infers this person is a leader in ASIC design and verification with extensive experience in managing complex projects.

Location: Ahmedabad, Gujarat, India

Experience: 29 yrs 6 mos

Skills

System Verilog
Vip Development
Hvl
Specman

Career Highlights

Expert in ASIC design and verification methodologies.
Led multiple successful VIP development projects.
Managed large teams across complex verification projects.

Work Experience

Intel Corporation

Verification Lead/Architect (1 yr 10 mos)

eInfochips

Director Engineering - ASIC (2 yrs 5 mos)

Delivery Manager (9 yrs 9 mos)

Sr. Tech. Lead (9 yrs 6 mos)

Sibridge Technologies

Sr. Member Technical Staff (2 yrs)

Inductotherm India Ltd

Design Engineer (4 yrs 1 mo)

Education

at Calorex Institute of Technology

Bachelor of Engineering at S. S. Engineering College

BE at University

Pranav Joshi

Director of Engineering

Ahmedabad, Gujarat, India29 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in ASIC design and verification methodologies.
Led multiple successful VIP development projects.
Managed large teams across complex verification projects.

Stackforce AI infers this person is a leader in ASIC design and verification with extensive experience in managing complex projects.

Contact

Skills

Core Skills

System VerilogVip DevelopmentHvlSpecman

Other Skills

Architecture designCustomer supportProject planningProject managementSoCASICPCIeFunctional VerificationModelSimNCSimUSBDebuggingEthernetC++Coverage Analysis

About

Experience

29 yrs 6 mos

Total Experience

6 yrs 11 mos

Average Tenure

1 yr 9 mos

Current Experience

Intel corporation

Verification Lead/Architect

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India

Einfochips

3 roles

Director Engineering - ASIC

Promoted

Feb 2022 – Jul 2024 · 2 yrs 5 mos

Delivery Manager

Promoted

May 2012 – Feb 2022 · 9 yrs 9 mos

Sr. Tech. Lead

Dec 2000 – Jun 2010 · 9 yrs 6 mos

Started as Design Engineer and contributed in IP Core development of IEEE1394.
In starting era of HVL, equipped myself with Specman and developed eRM Compliant PCI Express eVC for Verisity Inc [Now Cadence] as a project lead. During this time, i was responsible for developing Data Link Layer and Part of MAC layer. Also actively involved in Customer Supprt [6-7 Customers at time]. It was one of the best experience for me and now that turns in to one of my strong point..
Executed several Projects in System Verilog VIP development as Project Lead for team of 4 to 5 engineers.
Expertise on various HVL and methodology helps me to lead efficiently an ODC of 12-15 Team member for the verification of two generations of an SoC [FPGA] on time. I was responsible for project planning, tracking, review, regression analysis and development. Also helped for setting up ODC at offshore.
My experience in HVL leads me to manage + execute the VIP Development Program.
Multiple thread execution without any failures is my strength.

System VerilogHVLProject planningCustomer support

Sibridge technologies

Sr. Member Technical Staff

Jun 2010 – Jun 2012 · 2 yrs

Started as Sr. Member Technical Staff and looking after System Verilog VIP development program within organization.
Managing a pool of VIP like Ethernet, USB20, USB30, PCIE Gen1.0/2.0/3.0, AHB and AXI. All these VIPs are OVM, UVM and VMM compliant. Actively involved in the architecture of 10G, 40G Ethernet VIP enhancement and USB3.0 and PCIE3.0 VIP.
Directly managing methodology independent System Verilog library development program.
Interacting with Marketing team for the definition of the VIP product development literature and strategy.
Managing almost 15+ Engineers who are engaged in the development of various VIPs.
Involved in VIP support for couple of customers.
My immediate goal is to work on "How to leverage VIP development duration?" for complex protocol like USB30, PCI Express with quality and timely presence in market before IP starts floating.

System VerilogVIP developmentArchitecture designCustomer support