Venkatesh Degoud — Software Engineer

My work involves Physical Design closure (bakend) at block level implementation. Successfully converged design in latest technology node starting from RTL to final tape-in. Convergence of the design involved timing, layout DRC’s, quality fixes and various signoff checks. As a SOC Design Engineer worked on RTL-GDSII and my responsibilities includes, • Block level Physical Implementation which includes Synthesis, Floor-planning, Power Planning, Placement, CTS, Routing, timing closure, Quality fixes and other signoff checks. • Worked on different technology nodes (14nm, 10++nm, 10nm & 7nm). • Worked on various frequencies upto 4GHz. • Worked on analyzing and creation of Primary & Secondary Voltage areas. • Worked on block level optimal macro placement by using data flow analysis or automated macro placement approach using ICC/ICC2/FC/Innovus tools. • Performing physical aware Synthesis of the blocks. Applied different optimization techniques to achieve optimal synthesized netlist and QoR at synthesis stage. • Worked on partition having multimillion gate count which resulted in high congestion and cell/pin density. Applied different techniques at placement stage to resolve congestion issue and optimal logic placement. • Worked on CTS to achieve desired latency and skew target numbers for multiple high-speed clocks. • Applied different techniques to fix shorts, DRCs & miscellaneous verification checks at route stage. • Performed Engineering Change Orders (ECOs), implemented multiple complex functional ecos late in the design cycle, setup/hold conflict timing paths, crosstalk and quality fixes. • Providing the deliverables within the given time frame. Thank You, Regards, Venkatesh

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and SoC implementation.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 4 mos