Bhuvan Narasimhan

Software Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in timing and power convergence for ARM-based CPUs.
  • Proficient in scripting with Perl, TCL, and Python.
  • Strong background in physical design and VLSI.
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and timing analysis.

Contact

LinkedIn

Skills

Core Skills

StaPhysical Design

Other Skills

Synopsys PrimetimesynthesisVery-Large-Scale Integration (VLSI)CLinuxVHDLPythonTCLDFTPerl

About

Physical design engineer with experience in timing and power convergence of ARM based CPU cores , SoC blocks and discrete GPU | scripting in Perl, tcl and python.

Experience

8 yrs 8 mos
Total Experience
4 yrs 4 mos
Average Tenure
7 yrs 1 mo
Current Experience

Nvidia

2 roles

Senior Physical Design Engineer

Promoted

May 2020 – Present · 5 yrs 11 mos

STASynopsys PrimetimesynthesisVery-Large-Scale Integration (VLSI)Physical Design

ASIC Engineer

Mar 2019 – May 2020 · 1 yr 2 mos

Mediatek

STA Engineer

Jul 2017 – Feb 2019 · 1 yr 7 mos · Bengaluru, Karnataka, India

STA

Bendflex research and development private limited

Summer Intern

Jun 2016 – Jul 2016 · 1 mo · Electronic city, Bengaluru

Isro satellite center, bangalore

Project Trainee

May 2015 – Jul 2015 · 2 mos

Education

RV College Of Engineering

Bachelor of Engineering (BE) — Electronics and communication engineering

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Sta & Physical Design

Explore similar profiles based on matching skills and experience

MD

Mario Da Costa

Engineering Manager

at Intel Corporation

Bengaluru, India25 yrs 9 mos exp
Rahul Kumar Singh

Rahul Kumar Singh

Staff Engineer

at MediaTek

Bengaluru, India10 yrs 8 mos exp
MS

M Swathi

Talent Acquisition Specialist

at Biz Staffing Comrade Pvt Ltd

Bengaluru, India10 yrs 9 mos exp
RecruitingSourcing
Akhil Santhosh

Akhil Santhosh

Senior Physical Design Engineer

at Mirafra Technologies

Hyderabad, India3 yrs 5 mos exp
Physical VerificationStatic Timing Analysis
Animesh Pandey

Animesh Pandey

Staff Engineer

at Qualcomm

Noida, India10 yrs 8 mos exp
ASICStatic Timing Analysis
Shreenidhi Rama Krishna

Shreenidhi Rama Krishna

GPU Silicon PD Engineer, Staff

at Qualcomm

San Diego, United States10 yrs 7 mos exp
Physical DesignStatic Timing AnalysisProcess Control EngineeringSafety Systems DesignControl Logic Development
Shridhar Alure

Shridhar Alure

Staff Physical Design Engineer

at MediaTek

Bengaluru, India5 yrs 8 mos exp
Physical DesignVLSI
Heerak Bandopadhyay

Heerak Bandopadhyay

Senior Department Manager

at MediaTek

Bengaluru, India19 yrs 5 mos exp
ASICSoCPower IntegrityPower Analysis