SIVARAM ELURU

Software Engineer

Hyderabad, Telangana, India12 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Masters in Embedded Systems from BITS Pilani.
  • Hands-on experience with EDA tools and VLSI design.
  • Proven track record in VoIP development and FPGA projects.
Stackforce AI infers this person is a Semiconductor and Telecommunications specialist with strong VLSI and FPGA expertise.

Contact

Skills

Core Skills

Physical DesignSynthesisRtl DesignVoip Development

Other Skills

STATiming AnalysisDocumentationRTL to GDSII flowPerlTclUnixVoIPSIPC/C++SVNMatlabMicrocontrollersProgrammingDigital Electronics

About

I have done my Masters in Embedded Systems from BITS Pilani Goa Campus with CGPA: 7.558 I have hands on experience in the EDA tools like Cadence virtuoso, NC Verilog, Encounter, Mentor Graphics and Xilinx ISE, EDK and SDK and familiar with Synopsis I have worked on the programming languages like C, Verilog HDL I have done a couple of projects on FPGA(Interfacing the peripherals and also some image processing techniques) , General purpose processor(Designing of control path and Data path for basic Assembly instructions) RTL to GDSII flow, Physical Design, Verification (Writing test benches to RTL code) The areas of projects that I have worked mostly are on VLSI Design, Verification, VLSI Architecture, Embedded Systems, FPGA Development, ASIC, Image processing and DSP Apart from Academics I have done a active role in college level fests in my B. Tech and I have acted as a Co-ordinator in Convocation 2014 at BITS Pilani Goa Campus I am looking for a entry level position in the field of VLSI and FPGA domains

Experience

12 yrs 1 mo
Total Experience
3 yrs 1 mo
Average Tenure
7 yrs 2 mos
Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Jan 2024Present · 2 yrs 3 mos

  • Synthesis/Constraints/Low Power/LEC/CLP/STA

Senior Engineer

Feb 2019Jan 2024 · 4 yrs 11 mos

  • Synthesis/Constraints/Low Power/LEC/CLP/STA

Synopsys inc

2 roles

ASIC Physical Design Engineer

Mar 2017Feb 2019 · 1 yr 11 mos

  • Working on Synthesis as well as Physical design flow for ARC processor IPs
  • Responsible for handling complete flow from Synthesis to Signoff for ARC IPs
  • Worked on SPG(Synopsys Guidance) flow in ICC1 and ICC2
  • Worked on hierarchical as well as flat implementation of complex IP designs
  • Handled the Customer Benchmark requests and delivered the results within deadline
  • Worked on 16nm FFC and 28nm technology nodes
  • STA and solving the timing and congestion issues by exploring the tool options
  • Involved in documentation of Benchmark results as well as customer presentations and also the documentation of ARC physical design flow
SynthesisPhysical DesignSTATiming AnalysisDocumentation

ASIC Physical Design Intern

Feb 2016Feb 2017 · 1 yr

  • Working with Physical Design Team(ARC processors)
  • RTL to GDSII flow for ARC processors IP
  • Analysing the timing paths for maximum achievable frequency of processor cores
  • Worked on technology nodes like 16nm(GL,FFC) 28nm,40nm
  • Tools known: DC Compiler,IC Compiler(ICC1), Encounter,RTL Compiler, VCS
  • Scripting languages: Perl,Tcl
  • Operating system: Unix
RTL to GDSII flowTiming AnalysisPerlTclUnixPhysical Design+1

Polycom

Intern

Jan 2015Jun 2015 · 5 mos · Hyderabad Area, India

  • Worked on VoIP phones using SIP protocol for establishment of calls among phones by the use of the internet without the use of traditional PSTN
  • Fixing Software Issues of code written in C/C++
  • Get Familiar with SVN Code base and Build Server,Crucible,JIRA,Asterisk Server
  • Worked in Voice Development Team
  • Done Perl scripting for test cases
  • Skills Acquired: Linux,Perl
VoIPSIPC/C++SVNPerlVoIP Development

Birla institute of technology and science, pilani

2 roles

Professional Assistant

Feb 2014Dec 2014 · 10 mos · Goa

  • Maintain a database of all the passed out students from the college
  • Organize on-campus talks by Alumni
  • Facilitating Accommodation to the Alumni visiting the campus
  • Member of Convocation 2014 team

Masters Student

Jul 2013Jul 2015 · 2 yrs · Goa

  • I have done M. E EMBEDDED SYSTEMS at BITS Pilani Goa Campus

Education

Birla Institute of Technology and Science, Pilani

Master's degree — Embedded Systems

Jan 2013Jan 2015

Vignan Institute of Information and Technology

Bachelor's Degree

Jan 2009Jan 2013

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