Mouli Howladar

Product Engineer

Purba Bardhaman, West Bengal, India2 yrs 7 mos experience
Most Likely To Switch

Key Highlights

  • Strong foundation in chip design and testing.
  • Hands-on experience with DFT technologies.
  • Proficient in SystemVerilog, Verilog, and scripting.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and memory verification.

Contact

Skills

Core Skills

Memory DesignVerificationDftValidation

Other Skills

EspcvMonte Carlo SimulationTessentMbistIJTAGICLPDLVerdiTCADLinuxTCLJoint Test Action Group (JTAG)Physical DesignCadence VirtuosoStatic Timing Analysis

About

I’m currently working in the Memory Design team at Intel, with a completed M.Tech in Microelectronics and VLSI Design from MNNIT Allahabad. My journey into the semiconductor industry began with an internship at Intel, where I had the opportunity to work on DFT technologies like IJTAG, ICL, PDL, and MBIST validation. That experience gave me a strong foundation in the fundamentals of chip design and testing. Now, as part of the Memory Design team, I’m involved in both design and verification aspects of memory IPs. While my current focus is on functional verification, I’m also learning and contributing to design-related activities, aiming to grow as a well-rounded VLSI engineer. I enjoy solving technical challenges and have a good grasp of digital design, timing analysis, and debugging. I’m comfortable working with SystemVerilog, Verilog, and scripting languages like Python and Tcl to automate and optimize workflows. I’m passionate about technology and excited to keep learning and growing in the VLSI and semiconductor space. Looking forward to contributing to innovative and impactful solutions in this field.

Experience

2 yrs 7 mos
Total Experience
1 yr 3 mos
Average Tenure
1 yr 9 mos
Current Experience

Intel corporation

2 roles

Memory design verification engineer

Jun 2025Present · 11 mos · Bengaluru, Karnataka, India · Hybrid

EspcvMonte Carlo SimulationMemory DesignVerification

Graduate Technical Intern

Jul 2024May 2025 · 10 mos · Bengaluru, Karnataka, India · Hybrid

  • Domain - DFT
  • Validated JTAG/IJTAG per IEEE 1149.1 & 1687 standards.
  • Hands-on with IJTAG, ICL, PDL, and MBIST repair.
  • Analyzed fail data & redundancy; validated BISR logic.
  • Debugged DFT logic; solid in Scan, ATPG, and Boundary Scan.
TessentMbistDFTValidation

Motilal nehru national institute of technology

Teaching Assistant

Aug 2023Jun 2024 · 10 mos · Prayagraj, Uttar Pradesh, India · On-site

Education

Motilal Nehru National Institute Of Technology

Master of Technology - MTech — Microelectronics and VLSI

Aug 2023Jun 2025

Cooch Behar Government Engineering College

B.tech — Electronics and Communications Engineering

Jan 2018Jan 2022

Parulia kk High School

Intermediate — Science

Apr 2017Mar 2018

Parulia KK High School

10th

Jan 2015Feb 2016

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