Mandeep Singh — Software Engineer

• Full integration ownership of Smartphone SoC partition level activities and block level integration activities for IoT based projects. • 3nm,4nm,5nm,6nm,7nm,12nm finfet node and 160nm cmos node for analog dominant IPs and chips. • Hands on experience in debugging timing critical blocks. • Sub System level STA (pre-layout and post-layout). • Timing closure, Timing ECO. • PrimeTime, Tweaker. • Synthesis. • Design Compiler, Genus. • Conformal LEC • Worked with scripting languages like Perl, Shell, C.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC integration and timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 3 mos