Nov 2016 – Oct 2020 · 3 yrs 11 mos · Penang, Malaysia

• I'm the lead for Synthesis and STA team responsible for synthesis and timing signoff for full chip comprising 28 blocks, 11 subsystems. I handle everything from constraints setup, logical equivalence check, design for test logic insertion, pre-layout STA and even implement functional ECOs using Conformal ECO. I also co-ordinate with physical design engineers for the timing violations analysis and timing ECO iterations. I'm responsible for full chip signoff. I work with teams in different geographies, time zones.

Jan 2015 – Nov 2016 · 1 yr 10 mos · Bengaluru Area, India

• Signoff Timing for Modem

Aug 2012 – Dec 2014 · 2 yrs 4 mos · Hyderabad, Andhra Pradesh

• 1. Full Chip Netlisting which includes full chip quality checks before PD delivery.
• 2. Repeater Flop analysis at SOC level to ease timing on critical paths and help better floorplan.
• 3. Full chip connectivity checks between various Tiles.
• 4. StaticTiming Analysis at SOC level.
• 5. Low Power Tile Synthesis in DC-Topo.
• 6. Contributing to UPF at full chip Verdi - LP runs.

Jul 2010 – Aug 2012 · 2 yrs 1 mo · Cochin Area, India

• 1. Verilog RTL coding of Video formatting modules with asynchronous FIFO.
• 2. Lint checks on the design using Spyglass for sanity.
• 3. Work with verification team to fix functional bugs found.
• 4. Full chip Synthesis with Top down approach using Design Compiler with
• frequency of 600 MHz targeting 65nm technology.
• 5. Signoff Static Timing Analysis for Full Chip using PrimeTime which involves
• setting up STA environment, constraining the design, clock definitions,
• exceptions, timing checks for interfaces like LVDS, RGB, MIPI etc.
• 6. Formal verification using Cadence Conformal LEC between all the stages
• from RTL to netlist and netlist to netlist.
• 7. Implementing ECOs in RTL and post layout netlists.