Keertiprasad Kulkarni

CTO

Bengaluru, Karnataka, India16 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design and Timing Closure.
  • Proven track record in Low Power and High Performance Designs.
  • Strong background in Static Timing Analysis and Logical Synthesis.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing AnalysisFloorplanningTiming ClosureLogical Synthesis

Other Skills

STAClock Tree SynthesisPhysical VerificationPnRPV closureRoutingSynthesisPre-layout Timing AnalysisLogical Equivalence Check

About

Senior Technical Manager at Mediatek

Experience

16 yrs 10 mos
Total Experience
2 yrs 4 mos
Average Tenure
5 mos
Current Experience

Mediatek

Senior Technical Manager

Nov 2025 – Present · 5 mos · Bengaluru, Karnataka, India

Static Timing AnalysisFloorplanningSTAClock Tree SynthesisLogical SynthesisPhysical Design+2

Cadence design systems

2 roles

Senior Principal Application Engineer

Jul 2024 – Nov 2025 · 1 yr 4 mos · Bengaluru, Karnataka, India

Principal Application Engineer

Mar 2020 – Jul 2024 · 4 yrs 4 mos · Bengaluru, Karnataka, India

Intel corporation

SoC Design Engineer

Jun 2019 – Mar 2020 · 9 mos · Bengaluru, Karnataka, India

Qualcomm

Lead Engineer Senior

Mar 2017 – May 2019 · 2 yrs 2 mos · Bengaluru Area, India

  • Floorplan, PnR, STA, PV closure for Lower Power and High performance Designs on lower technology nodes
FloorplanningPhysical Design

Cadence design systems

2 roles

Lead Design Engineer

Promoted

Jul 2016 – Mar 2017 · 8 mos

Senior Design Engineer

Jun 2014 – Jun 2016 · 2 yrs

  • Part of Physical Design Implementation Team.

Qualcomm

Physical Design Engineer

Apr 2011 – Jun 2014 · 3 yrs 2 mos · Bengaluru Area, India

  • Part of Physical Design Team in Qualcomm India Pvt Ltd.
  • Involved in Chip Level, Hard Macro Level Timing Closure, Signoff.
  • Good understanding of Floorplanning, CTS, Routing.

Wipro technologies

ASIC Engineer

Jan 2010 – Jan 2011 · 1 yr · Bengaluru Area, India

  • Worked on Synthesis,Pre-layout Timing Analysis, Logical Equivalence Check at the block level as well as at the Top level.

Rv-vlsi design center

Trainee

Jan 2009 – Jan 2010 · 1 yr

Education

Gogte Institute of Technology

B.E (E & C) — E & C

Jan 2004 – Jan 2009

R.L.Sc College belgaum

P.U — Science

Jan 2002 – Jan 2004

RV -VLSI

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