Parichay Papnoi — Software Engineer
I am currently working as Senior Silicon Design Engineer, specialising in the Physical Design profile. I have hands-on experience with the complete Place and Route (PNR) flow for timing-critical and multi-voltage blocks. My expertise extends to both Static Timing Analysis (STA) and physical verification (phyv) cleanup. In 2020, I secured an All India Rank (AIR) of 560 in the Electronics and Communication Engineering (ECE) exam. I hold a Master’s degree in VLSI System Design from NIT Warangal, which has further strengthened my engineering skills and professional knowledge.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Delhi, India
Experience: 5 yrs
Skills
- Physical Design
Career Highlights
- Senior Silicon Design Engineer with extensive PNR experience.
- Master's degree in VLSI System Design from NIT Warangal.
- Achieved AIR 560 in ECE exam 2020.
Work Experience
AMD
Senior Silicon Design Engineer (1 yr 5 mos)
Silicon Design Engineer 2 (2 yrs 5 mos)
Co-Op Engineer (1 yr 1 mo)
Azcom Technology
Software Engineer(lte/nbIot PHY layer) (1 yr 2 mos)
Education
Master of Technology - MTech at National Institute of Technology Warangal
Bachelor of Technology at Dr Akhilesh Das Gupta Institute of Professional Studies
