Vallem hari charan — Software Engineer
CPU Power Lead Power characterization using PTPX/Power Artist for various CPU cores for different CPU benchmarks. Driving Power convergence(Dynamic and Leakage) and optimization. PMIC Buck Planning for CPUSS Rails. Silicon Correlation for Power and Vmin. Driving Throttling mechanism's/configurations for CPUSS. Inrush Mitigation with Sleep Staggering. IPF/Vector ownership for IR analysis. Physical Design : Netlist to GDSII Flow (Intel experience) (Netlist - Floor Planning - Placement - Clock-tree Synthesis - Routing - Design Verification - GDSII). Scripting Language : PERL & TCL familiar with : STA, low power concepts. EDA TOOLS: Synopsys IC COMPILER Synopsys DESIGN COMPILER Synopsys PTPX/Prime Power Power Artist
Stackforce AI infers this person is a semiconductor engineering expert with a focus on power management and physical design.
Location: East Godavari, Andhra Pradesh, India
Experience: 10 yrs 11 mos
Skills
- Power
- Physical Design
Career Highlights
- Expert in CPU power optimization and characterization.
- Proficient in physical design from netlist to GDSII.
- Strong background in EDA tools and scripting languages.
Work Experience
Arm
Staff Engineer (1 yr 5 mos)
Qualcomm
Sr lead engineer (CPU Power Lead) (3 yrs)
Engineer senior (3 yrs 4 mos)
Intel Corporation
GRAPHICS HARDWARE ENGINEER (physical design) (2 yrs)
Aditya Engineering College
asst professor (1 yr 10 mos)
Education
Master's Degree at Jawaharlal Nehru Technological university kakinada
Bachelor’s Degree at Jawaharlal Nehru Technological University
ssc at bala vidya nikethan
