Mallesh Balla

CEO

Bengaluru, Karnataka, India11 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT methodologies and ATPG.
Proven track record in silicon bring up and validation.
Strong programming skills in C, C++, and Perl.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and ATE methodologies.

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Skills

Core Skills

AtpgDftAte

Other Skills

DFT methodologiesTest coverage analysisGate level simulation debugSilicon bring upValidation DFT PatternsGate Level EmulationStatic Timing AnalysisScan InsertionPattern GenerationDRC issuesATPG Coverage improvementTest Methods DevelopmentMemory PoolingMemory SharingX mode Conversion Techniques

About

DFT: * Good experience on block and SOC level test pattern generation for SAF and TDF with Bypass/Edt. * Good experience in test coverage analysis. * STA Test mode Constraints definition * Experience with IJTAG(IEEE 1149.1) programming. * Gate level simulation debug with strong understanding of DFT methodologies and tooling * Good knowledge on scan insertion, compression. .test coverage analysis. * Direct experience in silicon bring up, debug and validation DFT features on ATE-Verigy 93k * Gate Level Emulation for scan patterns using Synopsis Zebu. ATE: * Implemented the characterization program on ATE across process corners, voltage and temperature (PVT) and evaluate product margin. *Writing Test Methods on Test Cases on 93K * Develop test programs based on test plans and developed test methods. * Professional experience in test development and test program implementation and test program optimization involving yield enhancement, data collection and analysis, test time reduction and test program release. engineering and Production support for final packages and final test documentation * VTRAN experience in pattern conversation. * Hands on experience on Perl, shell, C and C++ language.

Experience

11 yrs 11 mos

Total Experience

5 yrs 11 mos

Average Tenure

6 yrs 2 mos

Current Experience

Amd

2 roles

Member of Technical Staff

Jun 2025 – Present · 11 mos

Sr. Silicon Design Engineer

Mar 2020 – Jun 2025 · 5 yrs 3 mos

> SoC Level ATPG and Simulations Activities.
> Block level test pattern generation for SAF and TDF for EDT and EDT Bypass Patterns.
> Gate level simulation debug with strong understanding of DFT methodologies and tooling.
> Test coverage analysis.
> Direct experience in silicon bring up, debug and validation DFT Patterns on ATE-Verigy 93k.
> Gate Level Emulation for scan patterns using Synopsis Zebu
> Static Timing Analysis for Scan on Shift-Capture

ATPGDFT methodologiesTest coverage analysisGate level simulation debugSilicon bring upValidation DFT Patterns+3

Tessolve

2 roles

DFT Engineer

Promoted

Jun 2018 – Feb 2020 · 1 yr 8 mos

Design Engineer
Samsung, IN, Karnataka – Contractor
> Implemented and Validated Scan Insertion for OCC, COMPRESSION, P1500 Wrapper at both Block
and TOP level
>Worked on Generating Patterns for both Stuck at Faults & Transition Faults.
>Analyzing and Fixing DRC issues.
>Simulating the Patterns with Zero Delay
>Simulating the Patterns with MIN and MAX corners
>Worked on ATPG Coverage improvement
Design Engineer
Texas Instruments, IN, Karnataka – Contractor
>Worked on Generating Patterns for both Stuck at Faults & Transition Faults.
>Analyzing and Fixing DRC issues using Cadence Tools