Kiruthiga K — Software Engineer
Proficient in soc level clock planning. Primarily focused on creating balanced global clock tree to achieve optimized global latency and skew targets across interfaces.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in SOC clock planning and physical design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 7 mos
Skills
- Soc Clock Planning
- Physical Design
Career Highlights
- Expert in SOC level clock planning.
- Proficient in static timing analysis.
- Skilled in physical design and VLSI methodologies.
Work Experience
AMD
Sr.Silicon Design Engineer (8 mos)
Intel Corporation
Physical Design Timing Engineer (5 yrs 2 mos)
Graduate Technical Intern (11 mos)
Wipro Limited
Project Engineer (9 mos)
Education
Master of Technology - MTech at Vellore Institute of Technology
Bachelor of Engineering (B.E.) at Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College
