Dec 2018 – Mar 2020 · 1 yr 3 mos · Greater Hyderabad Area

Dec 2012 – Dec 2018 · 6 yrs · Greater Hyderabad Area

• Responsibilities:
• Verification of FPGA at Fabric , Micro-controller subsystem and IP levels.
• Defining Verification plans and coverage closure .
• Verification of FIC32 using UVM
• Verification of FPGA programming circuitry in block and fullchip level
• Verification of Physical unclonable function
• Verification of FPGA inbuilt resources and sub circuits.
• Verification of Production Firmware.
• Completed PCIE AXI overlay verification with Questa connect check.
• Completed PCIE register verification with RAL.
• Integrated of various QVIP in to top level verification environment.
• Updating tests as per updates in Firmware.
• Running and maintaining regressions.
• Understanding and providing work around/suggestions for SAR filed by other team members.
• Helping other team members with debugging and resolving their tasks.
• Environment: System Verilog, UVM, Questa, Questa Verification Manager, SVN repository , Assertions , Questa auto check , Questa connect check and assertions .
• Achievements & Contributions.
• Filed approximately 450 Bugs
• Four instant award and two spot award.
• MicroQuill award paper on “Variation of PCIE using InFact”.

Mar 2011 – Dec 2012 · 1 yr 9 mos · Greater Hyderabad Area

• Responsibilities:
• Created OVM based Environment for Arbiter block and integrated Mentor Verification Manager and functional coverage trend analysis for easy tracking.
• Created an Verilog based environment for Test FPGA, it consists of Avalon interface, CPRI & SRIO IP,s .
• Environment: System Verilog, OVM, Questa, Questa Verification Manager, SVN repository.
• Achievements & Contributions.
• Filed approximately 50 Bugs.

Aug 2009 – Mar 2011 · 1 yr 7 mos · Greater Hyderabad Area

• Responsibilities:
• Developing verification environment for programming/security subsystem verification and developing BMOD for the same.
• Developing of ENVM BMOD for verification of ENVM controller.
• Development of SOC system level test cases for Smart Fusion which is FPGA that integrate an FPGA, ARM CORTEX.
• Firmware verification of G4 integrator family.
• Environment: Verilog, Modelsim, Solaris, Simplify, Designer, Cadence schematic viewer & SVN repository.
• Achievements & Contributions.
• The models and test scenarios developed for ENVM and programming/security subsystem found out many critical bugs.
• G4 Integrator was successfully programmable on the first silicon.
• Firmware verification was a new task for me, this task was also time critical , I learned the required aspects quickly and completed the task successfully on time and also found out quality bugs.
• For my contributions in above tasks, company awarded me with extra Stocks.

May 2006 – Aug 2009 · 3 yrs 3 mos · Greater Hyderabad Area

• Responsibilities:
• Developing verification environment for programming/security controller verification and developing BMOD for the same.
• Verifying inbuilt FPGA resources.
• Logic Verification of Net lists.
• Debugging Net lists and RTL related issues.
• Writing new test cases for new modules added in different device families.
• Modifying existing environment as required making improvements for different families.
• Environment: Verilog, Modelsim, Solaris, Simplify, Designer, Cadence schematic viewer & SVN repository.
• Achievements & Contributions.
• Identified critical short comings in existing programming controller verification flow and I proposed a new verification strategy for which I was very appreciated, this new environment that I developed identified many bugs in design that went unnoticed in previous flow.
• Involved and successfully completed time critical tape out tasks for Igloo, Igloo Nano, Igloo Enhanced, Fusion & Fusion2 families FPGA.
• Because of my committed contributions towards project, I was absorbed by ACTEL during acquisition of Qualcore.

Aug 2005 – Apr 2006 · 8 mos · Greater Hyderabad Area

• Responsibilities:
• Stitching of all the sub blocks into top level block and making full system work.
• Synthesizing and generating Gate-Level net list.
• Design Implementation.
• Place and Route.
• Optimization to improve speed.
• Board bring up and board level debugging.
• Environment: Verilog, Xilinx series 8.1, Cadence NC Sim, Windows NT, Linux.
• Achievements & Contributions.
• My innovative ideas made DDR work on board.
• My proactive involvement in different stages of the project contributed to successful completion of full working project in expected time.
• Recognizing my efforts and contributions, organization gave me special retention bonus.