Venu Naik

Software Engineer

Andhra Pradesh, India10 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 7 years of experience in VLSI and formal verification.
  • Successfully completed 2 tapeouts in LEC.
  • Expert in low-power design and formal verification tools.
Stackforce AI infers this person is a VLSI design engineer with expertise in formal verification and low-power design.

Contact

Skills

Core Skills

Formal VerificationLow-power Design

Other Skills

FM ECOFM LPCLPsystem verilogVerilogVLSIFPGA prototypingFPGAElectronicsUVMASICVHDLCMatlabEmbedded Systems

About

I have overall 7 years of experience including 14 months of internship. Currently working as a Sr Application Engineer ll @ Synopsys India Pvt Ltd Hyd. worked as M.T.S in AMD India Pvt Ltd, And Completed 2 tapeouts in LEC( Formal Equivalence both power aware and non- power Aware) I did M.Tech From Indian Institute of Technology(BHU) varanasi with an CGPA of 8.4/10. Language: VERILOG,SYSTEM VERILOG TOOLS: Formality, Conformal, VCLP, Design Compiler, VIRTUOSO, Innovus

Experience

10 yrs 6 mos
Total Experience
2 yrs 3 mos
Average Tenure
3 yrs 6 mos
Current Experience

Synopsys inc

4 roles

Staff Engineer

Promoted

Nov 2023Present · 2 yrs 6 mos

Staff Field Application Engineer

Nov 2022Dec 2025 · 3 yrs 1 mo

  • Was part of Intel field support team supporting Formality , formality Low power And Formality ECO ( Targeted Synthesis which is a RTL 2 Netlist ECO flow) .
  • Part of the team where we successfully able to make Formality as signoff tool
FM ECOFM LPFormal VerificationLow-power Design

Sr Application Engineer II

Nov 2020May 2022 · 1 yr 6 mos

FM ECOFM LPFormal VerificationLow-power Design

Sr Application Engineer I

Aug 2018Nov 2020 · 2 yrs 3 mos

Amd

Member Of Technical Staff

Jun 2021Nov 2022 · 1 yr 5 mos · India

  • Responsible for LEC signoff checks for 225 blocks from RTL to DFT inserted Netlist with both power and non power aware verification. and Repeater LEC or Feedthrough verification.
FM ECOFM LPFormal VerificationLow-power Design

Amd

CAD Design Engineer II

Sep 2017Aug 2018 · 11 mos · Hyderabad Area, India

Cadence design systems

Sr Application Engineer

Oct 2015Aug 2017 · 1 yr 10 mos · India

  • worked as FEV engineer Supporting Qualcomm

Education

IIT(BHU) VARANASI

Master's Degree

Jan 2011Jan 2013

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