Maninder Kaur — CEO

• Physical Design Intern at Synopsys Bangalore. • Hands on experience with Synthesis, P&R and sign-off tools – Design Compiler • IC Compiler-II, Primetime and Primerail. • VHDL, Verilog / System Verilog • Good understanding of ASIC backend flow from RTL to GDSII. • Familiarity with timing and power analysis. • Mentor Questa Sim and Xilinx ISE • LabVIEW and MATLAB

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC physical design and verification.

Experience: 9 yrs 8 mos