Shreevatsa M

Software Engineer

Karnataka, India10 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in IO circuit design and VLSI.
  • Proficient in Cadence Virtuoso and custom compiler tools.
  • Strong background in Verilog-A scripting.
Stackforce AI infers this person is a VLSI design engineer with expertise in IO circuit design.

Contact

LinkedIn

Skills

Other Skills

IO DesignCadence Virtuosocustom compilerVery-Large-Scale Integration (VLSI)Verilog-AMOSFET

About

Design engineer with experience of LVDS, DDR2, LVCMOS-GPIO(overvoltage) and other IO design Tools: Cadence-Virtuoso, Synopsis-Custom Compiler Skills: VerilogA script

Experience

10 yrs 10 mos
Total Experience
5 yrs 5 mos
Average Tenure
5 yrs 9 mos
Current Experience

Amd

Sr. Circuit design engineer

Aug 2020 – Present · 5 yrs 9 mos · Bengaluru, Karnataka, India

Sankalp semiconductor

IO Circuit Design Engineer

Jul 2015 – Aug 2020 · 5 yrs 1 mo

Education

SJEC

Engineer’s Degree — Electronics and Communications Engineering

Jan 2011 – Jan 2015

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