Oct 2019 – Aug 2022 · 2 yrs 10 mos

Jan 2018 – Oct 2019 · 1 yr 9 mos

Dec 2016 – Dec 2017 · 1 yr · Bengaluru, Karnataka, India

Jul 2015 – Jan 2016 · 6 mos · Bangalore

• Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Budgeting, Clock Tree planning & analysis, Placement, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
• sound knowledge in EDA tools such as DC, ICC,PT internal tools & flow, etc.
• Worked closely with the design team throughout the project life cycle to debug issues & implement the physical design in the most efficient way to save Power, Area & achieve High performance.
• Worked closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow.
• Understanding of Timing constraints, SI prevention, Power reduction.
• I have prior experience with Synopsys and route tools.
• I completed design on 180nm.
• Proficient in Linux/TCL/Perl.
• Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability.