S V Veera Kanmani

Software Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in design verification across multiple companies.
Strong foundation in Verilog and functional verification methodologies.
Proven track record in engineering roles within top tech firms.

Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and telecommunications industries.

Contact

Skills

Core Skills

Functional VerificationDesign Verification

Other Skills

VerilogTelecommunicationsMatlabUniversal Verification Methodology (UVM)SystemVerilogC (Programming Language)Python (Programming Language)C++Object-Oriented Programming (OOP)LinuxMATLAB

About

done a 4 months of internship in inautix technologies, Chennai done a 6 months of internship in CFAST, LRDE, DRDO, Bangalore Open for design verification profile

Experience

7 yrs 7 mos

Total Experience

1 yr 8 mos

Average Tenure

3 yrs 9 mos

Current Experience

Microchip technology inc.

Senior verification engineer I

Aug 2022 – Present · 3 yrs 9 mos · Bangalore Urban, Karnataka, India

Tessolve

Design engineer I

Apr 2022 – Aug 2022 · 4 mos · Bangalore Urban, Karnataka, India

Spicaworks

Verification Engineer

Feb 2021 – Mar 2022 · 1 yr 1 mo · Bangalore Urban, Karnataka, India

VerilogFunctional Verification

Mediatek

Verification Engineer (Contract)

Feb 2021 – Mar 2022 · 1 yr 1 mo · Bangalore Urban, Karnataka, India

VerilogFunctional Verification

Qualcomm

Design Verification Engineer

Jul 2018 – Dec 2020 · 2 yrs 5 mos · Greater Chennai Area

VerilogDesign Verification

Education

PSG College of Technology

Master of Engineering - MEng — communication systems

Jan 2016 – Jan 2018

Thiagarajar College of Engineering

Bachelor of Engineering - BE

Jan 2012 – Jan 2016

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