Hardik Doshi

DevOps Engineer

Bengaluru, Karnataka, India13 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Digital and Mixed Signal Verification.
  • Proficient in UVM and e-RM Verification Environments.
  • Strong background in RTL and Functional Verification.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Digital and Mixed Signal Design.

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Skills

Core Skills

VerificationAnalog & Mixed Signal Design VerificationRtl Validation

Other Skills

PIPE ProtocolTest case developmentVerification EnvironmentCode CoveragePerlShell ScriptingTest Pattern GenerationVerilogEmbedded ProductsMicro-controllerGSM TechnologyC LanguageVHDLVLSIDigital Electronics

About

Hands on IP Design Verification (Digital and Mixed Signal Verification) Hands on UVM/e-RM Verification Environment Functional and Code Coverage closure and analysis Knowledge of System Verilog and Specman-e Verilog behavioural/Real number models Knowledge of System Verilog and Specman-e Good Understanding of Front-End Design and RTL Automation of Design using Shell and Perl Scripting Skills:- USB 3.0 and PCI-e (PIPE) PHY level protocol Functional/mixed verification of PIPE PHY level protocol Good Knowledge of System verilog/verilog/e-langague/wreal Code and Functional Coverage analysis and developed directed test cases for holes Verification of Memory Test-chip Analog and Mixed Signal Verification of PIPE PHY level protocol Memory Functional Faults and Testing Algorithms

Experience

13 yrs
Total Experience
3 yrs 3 mos
Average Tenure
4 yrs 2 mos
Current Experience

Amd

2 roles

Senior Member of Technical Staff

Promoted

Jul 2024Present · 1 yr 10 mos · Bengaluru, Karnataka, India · Hybrid

Member Of Technical Staff

Feb 2022Jun 2024 · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Cadence design systems

2 roles

Lead Design Engineer

Promoted

Jul 2018Feb 2022 · 3 yrs 7 mos

Design Engineer II

Jan 2015Jul 2018 · 3 yrs 6 mos

  • Knowledge of PIPE IP (PCIe & USB-3.0 Protocols PHY Level) , Verification of RTL level and Gate Level (PIPE Protocol PHY Level), Development and Modification of Test case, Modification of Verification Environment (eRM/UVM) as per project requirements, Knowledge of Spacman-e, Verilog Functional Models, Knowledge of Code Coverage, Analog & Mixed Signal Design Verification of PIPE Protocols, Perl and Shell Script (Automation)
PIPE ProtocolVerificationTest case developmentVerification EnvironmentCode CoverageAnalog & Mixed Signal Design Verification+2

Stmicroelectronics

Intern

Jul 2013Jun 2014 · 11 mos · Greater Noida

  • Work Done at STMicroelectronics:-
  • Developed Automatic Tool for Test Pattern generation
  • RTL Validation of Memory Test Chip Design
  • Working on Test pattern of Test Chip
  • Verilog Memory Models Modification
Test Pattern GenerationRTL ValidationVerilog

Devindia infoway

Embedded Developer

Sep 2011Jul 2012 · 10 mos · Rajkot

  • Developed the Embedded Products based on the Micro-controller and GSM Technology with used as Firmware of C Language
Embedded ProductsMicro-controllerGSM TechnologyC Language

Education

Nirma Institute Of Technology

Master of Technology (M.Tech.) — VLSI

Jan 2012Jan 2014

Atmiya Institute of Technology and Science

Bachelor of Engineering (B.E.)

Jan 2007Jan 2011

Vivek High School

H.S.C — Science

Jan 2005Jan 2007

G.T. Sheth High School

S.S.C — General Studies

Jan 1997Jan 2005

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