Hardik Doshi — DevOps Engineer
Hands on IP Design Verification (Digital and Mixed Signal Verification) Hands on UVM/e-RM Verification Environment Functional and Code Coverage closure and analysis Knowledge of System Verilog and Specman-e Verilog behavioural/Real number models Knowledge of System Verilog and Specman-e Good Understanding of Front-End Design and RTL Automation of Design using Shell and Perl Scripting Skills:- USB 3.0 and PCI-e (PIPE) PHY level protocol Functional/mixed verification of PIPE PHY level protocol Good Knowledge of System verilog/verilog/e-langague/wreal Code and Functional Coverage analysis and developed directed test cases for holes Verification of Memory Test-chip Analog and Mixed Signal Verification of PIPE PHY level protocol Memory Functional Faults and Testing Algorithms
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Digital and Mixed Signal Design.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs
Skills
- Verification
- Analog & Mixed Signal Design Verification
- Rtl Validation
Career Highlights
- Expert in Digital and Mixed Signal Verification.
- Proficient in UVM and e-RM Verification Environments.
- Strong background in RTL and Functional Verification.
Work Experience
AMD
Senior Member of Technical Staff (1 yr 10 mos)
Member Of Technical Staff (2 yrs 4 mos)
Cadence Design Systems
Lead Design Engineer (3 yrs 7 mos)
Design Engineer II (3 yrs 6 mos)
STMicroelectronics
Intern (11 mos)
DevIndia Infoway
Embedded Developer (10 mos)
Education
Master of Technology (M.Tech.) at Nirma Institute Of Technology
Bachelor of Engineering (B.E.) at Atmiya Institute of Technology and Science
H.S.C at Vivek High School
S.S.C at G.T. Sheth High School