Palwai Sandeep

Software Engineer

Hyderabad, Telangana, India4 yrs 7 mos experience

Key Highlights

  • Experienced in RTL design and automation using Python.
  • Proficient in Logic Synthesis and Digital Design methodologies.
  • Strong background in ASIC and FPGA development.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and Logic Synthesis.

Contact

LinkedIn

Skills

Core Skills

Logic Synthesis

Other Skills

CDCDigital DesignsSynopsys FormalityDC CompilerTCLSynopsys toolsVerilogPython (Programming Language)Field-Programmable Gate Arrays (FPGA)Design compilerDigital ElectronicsRTL DesignLECUPFLint

About

Working as RTL design engineer and also automating works with pythons scripts.

Experience

4 yrs 7 mos
Total Experience
2 yrs 9 mos
Average Tenure
1 yr 10 mos
Current Experience

Qualcomm

Senior Engineer

Jun 2024 – Present · 1 yr 10 mos · Hyderabad, Telangana, India

Amd

3 roles

Sr. Silicon Design Engineer

Promoted

Jul 2023 – Jun 2024 · 11 mos

CDCLogic Synthesis

Silicon Design Engineer-2

Sep 2021 – Jul 2023 · 1 yr 10 mos

Logic SynthesisDigital Designs

RTL Design

Nov 2020 – Sep 2021 · 10 mos

  • Internship

Education

Vasavi College of Engg

Master of Engineering - MEng — Embeded and VLSI

Jan 2019 – Jan 2021

Sreenidhi Institute of Science and Technology

Bachelor's degree

Jan 2016 – Jan 2019

Government institute of electronics

Diploma of Education — Electronics and Communications Engineering

Jul 2012 – Dec 2015

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