Jun 2023 – May 2024 · 11 mos · Bengaluru, Karnataka, India · Remote

• DFT Project Head handling multiple client requirements.

Jan 2022 – Sep 2022 · 8 mos · Bengaluru, Karnataka, India · Remote

• DFT Project head handling multiple client requirements.

Sep 2022 – Jun 2023 · 9 mos · Bengaluru, Karnataka, India · On-site

• Scan Insertion for Serdes blocks and Die-Die blocks.

Feb 2020 – Jan 2022 · 1 yr 11 mos · Bengaluru, Karnataka, India

• SoC and block-level ATPG Validation(tmax) and GLS(ncsim) for Stuck-At, Transition, Bypass, Bridging, Dynamic Bridging, Xtol, pof, Burnin, Extest pattern types(also netlist independent patterns).
• Synopsys diagnosis automation that can be used for any block/core.
• Pattern Porting using StilGen, SpfGen. Probe strobe data handling.
• IR Drop pulse_e pulse_r fsdb generation and analysis.
• Synthesis db compilation and strategy estimation, Floor-planning, Power planning, Global routing, Clock tree synthesis, Placement and Routing (PnR), Detailed routing and timing check, and slack improvement, Vtswap, upsizing/downsizing, signal integrity, and Layout using OpenLane. RTL2GDS Magic, Yosys, abc, OpenSTA, OpenROAD, TritonRoute.

Jun 2017 – Jan 2020 · 2 yrs 7 mos · Bengaluru Area, India

• Intel’s ring based hierarchical Endpoint based Scan Subsystems using Structural Fabric Test(STF) as well as Intel Test Pattern Processors(ITPP) and their simulations in Intel’s Graphics & Throughput Computing Hardware Engineering (GTCHE) Division that’s responsible for the design and development of Graphics, Media and Display IPs as well as discrete Graphics SoC products (GPUs), targeting the Datacenter and Client markets for next-generation applications such as High-performance Exascale computing, Deep learning, Cloud Graphics, Media analytics, High-end gaming, etc.
• EDT and ATPG for StuckAt, Atspeed, RAM Sequential faults, Timing Simulations. ITPP validation and issue debug.
• DFx design and MBIST Implementation for mutli-port ultra high density high speed memories at (CIG) Intel team. ATPG for StuckAt, Atspeed, RAM Sequential faults, Timing Simulations. MBIST Implementation and Verification of ROMs, SRAMs and Ultra High Density Multi Port RAMs
• Tools used:
• Tessent ETChecker, ETPlanner, ETAssemble, ETSignOff and ETVerfiy, also .svf DVE Sims.
• DFx design and implementation for x4, x8, x16 data lane IPs belonging to PCI Express card for ICeLake and TiGerLake at (MIG) Intel team. Scan Insertion using design compiler and fastscan atpg for Sa, TF and sdc reading for mcp pattern masking.
• Tools used: Synopsys DC, Tessent TestKompress, DFTMAX, TestMAX, NCsim, VCS.
• extra learning: RISC-V Microprocessor design using C++, Python.

Jun 2015 – May 2017 · 1 yr 11 mos · Bengaluru Area, India

• Design Test implementation for high precision ADC, CRC, BandGap reference, CRM, HDR imaging. CMOS Image Sensors feature validation Otpm val and suite automation. Image processing
• PVT lot analysis, wafer field issue, Issue reproduction and correlation.
• Limit tuning, Mass production Data Analysis and Yield improvement using ANOVA/Six Sigma.