Jun 2019 – Mar 2024 · 4 yrs 9 mos · Greater Bengaluru Area

• Silicon Solutions Architect
• Low power synth flow architected and developed from scratch using a combination of automation platforms including Python, TCL and Cadence Genus tool and Synopsys Fusion Compiler tool. Deployed across 5 projects.
• Demonstrated 20% runtime improvement across multiple blocks.
• Silicon Constraints Flow architect and development that eliminates constraints generation, management and verification effort across SoC and IPs, with runtime and compute/Resource optimization worked closely with the sales, legal and licenses team.
• First CAD Engineer in Gchips India site, contributed across all CAD flows at Gchips.
• Worked on release flows.

Dec 2017 – Apr 2019 · 1 yr 4 mos · Bengaluru, Karnataka, India

• Flow Development and Maintenance:
• 1) Integration of ASIC timing constraints in Emulation Environment:
• Eliminates constraints writing effort across SoC and IPs in Emulation Environment, which is
• much different then ASIC, with runtime and compute/Resource optimization.
• Flow is developed from scratch using combination of Python language and TimeVision tool
• after benchmarking many other solutions. Solution validated on 10+ IPs belonging to 2 SoCs.
• 2) World Wide owner of 3 flows on timing constraints:
• 20+ Major feature addition and their deployment in 7+ SoC [Nodes 7nm,8nm,10nm,14nm]
• using Python, Perl and TCL.
• Based on Timing Constraints lint, Formal verification of FP, MCP for early timing closure, Clock
• leakage identification, PPA improvements etc.
• Focused on checking completeness and consistency of synthesis and timing-tool constraint
• files to reduce iterations in a chip design flow.
• Initiatives:
• 1) RTL2Netlist cycle optimization for early PD closure:
• Brought the RTL2Netlist implementation cycle time from 21 days to 16 days
• By enabling RTL based timing constraints demotion and clock report generation for MBIST.
• Deployed in 1 SoC.
• 2) Clock Leakage Reduction:
• Wrote Tcl based script to identify clock leakage early in the cycle.
• Wrote Stop sense based and other timing constraints to stop clock leakage and achieve
• better PPA.
• Misc:
• 1) Utility Contribution in synthesis flow, UPF quality checking flow.
• 2) Library comparison script.
• 3) Worldwide support for Constraint Management system.
• 4) Provided 5 training sessions to SoC teams for flow usage and setup.

Jul 2016 – Dec 2017 · 1 yr 5 mos · Bengaluru, Karnataka, India

• Worked on development and world wide deployment of Constraints consistency checking methodology and Constraints quality checking using tools like Timevision and fishtail.
• Partnered with MBIST team and design to reduce RTL2NETLIST timeline by 2 days in each stage.
• Owner of constraints demotion flow.

Jun 2015 – Aug 2015 · 2 mos · Greater Bengaluru Area

• 1) Worked on developing regressions to test Clock Gating mechanism-based power reduction, provided by Powerpro from Mentor Graphics.
• 2) Created a perl Code to perform checks on clock frequency plan xls sheets.

Jun 2014 – Sep 2014 · 3 mos · Noida, Uttar Pradesh, India

• Learned about Verilog, FPGA and CMOS.
• Implemented basic - ALU, a circuit with multipath and false path.

Nov 2013 – May 2015 · 1 yr 6 mos · Greater Delhi Area

• Organised 3 workshops
• 1. Texas Instruments Beagle Bone Black
• 2. CUDA workshop by NVIDIA
• 3. Robotics workshop

Jun 2013 – Aug 2013 · 2 mos · Greater Delhi Area

• Made Touch Screen Controlled bot using ATmega 32.
• Made Visitor Counter.

Sep 2012 – May 2015 · 2 yrs 8 mos · Greater Delhi Area

• Represented class for 3 continuous years.