ABHISHEK KUMAR GUPTA

CEO

Delhi, India7 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in System Verilog and UVM for RTL verification.
  • Successfully verified GDDRx Memory Subsystem for Intel GPUs.
  • Strong collaboration skills in semiconductor engineering projects.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in RTL and memory subsystem verification.

Contact

Skills

Core Skills

Rtl VerificationSystem Verilog

Other Skills

AMBA ProtocolsDDR SDRAMUVMCommunicationFPGAProduct DesignTest PlanningAssertionsProblem SolvingAPBI2C ProtocolDebugging CodeMemory TestMicrosoft OfficePowerPoint

About

As a Design Verification Engineer at Intel Corporation, I have done my MTech in IEC (Integrated Electronics and Circuits) from IIT Delhi and expertise in System Verilog, UVM, and RTL Verification to ensure product quality and reliability. I have developed and executed verification plans for the GDDRx Memory Subsystem in Intel ARC GPUs, achieving coverage goals and meeting design requirements. Additionally, I’ve engineered scoreboards to validate design integrity and boost performance. With proficiency in protocols like APB, AXI, RNI, DFI, and UFI/CXL, I adapt to various project needs and collaborate effectively with teams. I’m eager to contribute to innovative projects and continue growing in semiconductor engineering.

Experience

7 yrs 1 mo
Total Experience
2 yrs 10 mos
Average Tenure
1 yr 5 mos
Current Experience

Cadence design systems (india) pvt. ltd.

Lead Design Engineer

Dec 2024Present · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

Soc Design Verification Engineer

Aug 2021Dec 2024 · 3 yrs 4 mos · Bangalore Urban, Karnataka, India · Hybrid

  • Working on GDDRx Memory Subsystem Verification for Intel ARC GPU family of products.
AMBA ProtocolsDDR SDRAMRTL VerificationSystem Verilog

Jio

Assitant Manager

Jul 2016Nov 2018 · 2 yrs 4 mos · Mumbai, Maharashtra, India

Communication

Bhaba atomic research center

Summer Intern

May 2015Jul 2015 · 2 mos · Mumbai Metropolitan Region

  • Got a handful of knowledge and experience in information about the Atomic criteria of material. Developed a scalar time module device with the help of FPGA kit and other electronic euipment devices which is used to calculate the number of neutron beams in specific time and variations in beams. Help of this both criteria and using Brag'law, we can study the crystallographic structure of material.
CommunicationSystem Verilog

Education

Indian Institute of Technology, Delhi

Master of Technology - MTech — VLSI and Microelectronics

Jan 2019Jan 2021

National Institute of Technology Jamshedpur

Bachelor's degree

Jan 2012Jan 2016

Stackforce found 100+ more professionals with Rtl Verification & System Verilog

Explore similar profiles based on matching skills and experience