S

Satheesh kumar

Software Engineer

Bangalore, Karnataka, India12 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led a verification team for PCIE GEN5 Tester.
  • Expert in UVM and SystemVerilog methodologies.
  • Strong background in RTL design and verification.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in PCIe and UVM methodologies.

Contact

LinkedIn

Skills

Core Skills

VerificationTest Plan

Other Skills

PCIE GEN5Test Case DevelopmentRegression DebuggingCode Coverage AnalysisSystemVerilogUVMVerilogASICRTL DesignDigital Circuit DesignVLSIXilinx ISEModelSimFunctional VerificationEDA

About

HDL : Verilog HVL : SystemVerilog Verification Methodologies : UVM Editors : GVIM/VI Editors EDA Tools : Xcelium, Questasim, Modelsim and ISE Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, STA ,SVA Scripting Language : Perl, python Protocol knowledge : AMBA APB, AHB, AXI3 ,PCIE gen5

Experience

12 yrs 4 mos
Total Experience
2 yrs 3 mos
Average Tenure
2 yrs 5 mos
Current Experience

Samsung r&d institute india

Senior Staff Engineer

Dec 2023 – Present · 2 yrs 5 mos

Mobiveil inc.

2 roles

Lead Engineer

Nov 2020 – Dec 2023 · 3 yrs 1 mo

  • PCIE GEN5 Tester verification
  • Responsibilities
  • Currently Leading verification team of 8 members
  • Responsible for integration and developing the environment.
  • Responsible for creating test plan and verification plan.
  • Responsible for developing Test case in SV for block level.
  • Debug the regression failures, report and file bugs.
  • Responsible for code coverage analysis and closure.
PCIE GEN5VerificationTest PlanTest Case DevelopmentRegression DebuggingCode Coverage Analysis

Senior Engineer

Jan 2020 – Nov 2020 · 10 mos

Amd

2 roles

SOC verification engineer

Aug 2017 – Jan 2020 · 2 yrs 5 mos · Hyderabad Area, India

SOC verification Engineer

Feb 2016 – Jul 2017 · 1 yr 5 mos · Hyderabad Area, India

Adeptchips

Verification Engineer

Dec 2015 – Jul 2017 · 1 yr 7 mos · Bangalore

Infosemi technologies

Verification Engineer

Aug 2014 – Dec 2015 · 1 yr 4 mos · Noida Area, India

Maven silicon

Verification engineer trainee

Mar 2013 – Nov 2013 · 8 mos · bangalore

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