Abhishek -

CTO

Bengaluru, Karnataka, India7 yrs 4 mos experience

Key Highlights

Expert in advanced semiconductor technologies.
Proficient in Cadence Virtuoso and verification tools.
Strong background in layout design for cutting-edge processes.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in advanced layout design technologies.

Contact

Skills

Core Skills

Layout Versus Schematic (lvs)Design Rule Checking (drc)

Other Skills

SimulationsDigital ElectronicsAnalog Circuit DesignStandard cell layoutVery-Large-Scale Integration (VLSI)ElectronicsDesign for ManufacturingVirtuosoCadence VirtuosoCadence SpectreCMOSCadence

About

Digital layout design engineer with a demonstrated history of working in the semiconductor industry. Skilled in Cadence Virtuoso Layout Editor, verification tools and Electronics. Expertise in mosfet and finget technology. Experience in tmsc 3nm finfet technology and 2nm GAAFET Technology. Strong engineering professional with a B.Tech focused in Electronics and Communications Engineering from Silicon Institute of Technology (SIT), Bhubaneswar.

Experience

7 yrs 4 mos

Total Experience

2 yrs 6 mos

Average Tenure

4 mos

Current Experience

Hcltech

2 roles

Technical Lead

Jan 2026 – Present · 4 mos

Lead Engineer

Oct 2021 – Feb 2026 · 4 yrs 4 mos

Layout Versus Schematic (LVS)Design Rule Checking (DRC)

Qualcomm

Digital layout design

Oct 2023 – Mar 2025 · 1 yr 5 mos · Bengaluru

Have worked on Samsung 3nm MBCfet technology to design std cell libraries.

Intel corporation

Layout Designer

Apr 2023 – Sep 2023 · 5 mos · Bengaluru, Karnataka, India · Remote

Google

Layout Design Engineer

Sep 2022 – Mar 2023 · 6 mos · Bengaluru, Karnataka, India

Working in std cell domain as a layout engineer. Working on 3nm TSMC finfet technology for layout designing of bit cell and flip flops.

Microchip technology inc.

Project Lead

Dec 2021 – Sep 2022 · 9 mos · Bengaluru, Karnataka, India

working as a STD cell layout engineer on various techniques like 40nm, 65 nm

Stmicroelectronics

std Cell design and layout

Oct 2019 – Nov 2021 · 2 yrs 1 mo · Greater Delhi Area

Have worked on standard cell circuit design, layout design, cell verification and circuit simulation for various drive strengths in 40nm, 90nm and 130nm technology.