Krishna Teja — Software Engineer
Having Good experience in Physical Design from synthesis to timing sign off, ASIC Layout Design and Verification from scratch level to top level in memory compiler and custom memories, and custom Analog blocks . Working in lower node technologies (5nm,7nm,10nm,16n)
Stackforce AI infers this person is a VLSI design engineer specializing in ASIC and physical design.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 4 mos
Skills
- Asic
- Physical Design
- Low-power Design
Career Highlights
- Expertise in Physical Design and ASIC Layout.
- Experience with lower node technologies down to 5nm.
- Proficient in Static Timing Analysis and Low-power Design.
Work Experience
IBM
Physicial Design Engineer (1 yr 9 mos)
AMD
Member of Technical Staff (1 yr 3 mos)
Intel Corporation
SoC Design Engineer (3 yrs 6 mos)
BlackPepper Technologies Pvt Ltd
Senior Asic Design Engineer (1 yr 2 mos)
Qualcomm
Layout Design Engineer (2 yrs)
Layout Engineer (2 yrs)
SiCon Design Technologies Pvt. Ltd.
Design Engineer (1 yr 1 mo)
DXCorr Design Inc
Member Of Technical Staff (1 yr 7 mos)
AMTS (2 yrs 4 mos)
Education
B.Tech at chebrolu engineering college
Bachelor's degree at gowtahm junior college
