F

Faimeem Naik

Software Engineer

Bengaluru, Karnataka, India8 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Analog Layout Design for advanced technology nodes.
  • Proficient in Cadence tools for layout verification.
  • Experience with multiple protocols including PLL and DDR.
Stackforce AI infers this person is a skilled Analog Layout Design Engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Analog Layout DesignCadence Virtuoso

Other Skills

PLL7nm technology node5nm technology node14nm technology node10nm technology nodeDDRGPIO45nm technologyLow Dropout RegulatorBGRDesign Rule Checking (DRC)Layout Versus Schematic (LVS)GenesysVerilog14nm

About

Technology nodes-Intel -10nm, 14nm, CMOS- 45nm, 180nm, TSMC- 5nm, 7nm Tools- Cadence, Genesys. Flows- DRC, LVS, Density, MRC, ERC, EM, IR, Antenna, Latchup etc. Has done Floorplaning and routing of blocks and subblocks of PLL, BGR, opamp, currents mirrors, voltage follower, IO, comparator etc. Protocol - DDR, OPIO, PLL.

Experience

8 yrs 10 mos
Total Experience
3 yrs 1 mo
Average Tenure
7 yrs 7 mos
Current Experience

Amd

Analog Layout Design Engineer at AMD through Juntran Technologies.

Jan 2020 – Present · 6 yrs 4 mos · Bengaluru, Karnataka, India

  • Working on PLL and other protocols for 7 and 5nm technology node.
PLL7nm technology node5nm technology nodeAnalog Layout DesignCadence Virtuoso

Sankalp semiconductor

Analog Layout Design Engineer at Sankalp Semiconductor through Juntran Techonologies

Jan 2019 – May 2019 · 4 mos · Hubli, Karnataka, India

  • Worked on 14 and 10 nm technology node for Intel , worked on protocol such as DDR and GPIO.
14nm technology node10nm technology nodeDDRGPIOAnalog Layout DesignCadence Virtuoso

Juntran technologies pvt ltd

Analog and Mixed Signal Layout Engineer

Oct 2018 – Present · 7 yrs 7 mos

Mirafra technologies

Analog Layout Design Engineer

May 2018 – Oct 2018 · 5 mos · Bengaluru, Karnataka, India

  • Worked on 45nm, worked on projects such as Low Dropout Regulator and its subblocks and BGR and its subblocks.
45nm technologyLow Dropout RegulatorBGRAnalog Layout DesignCadence Virtuoso

Accenture in india

Associate Engineer

Jul 2017 – May 2018 · 10 mos · India

Education

Visvesvaraya Technological University

Bachelor of Engineering - BE

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