Amit Gaikwad — Backend Engineer
Experienced SoC Design Verification Engineer with 8.10 years of expertise in full-chip verification using C, SystemVerilog, and UVM methodologies. Strong background in verifying processors, subsystems, and complex SoC architectures with proven hands-on experience in low-power verification scenarios and coverage closure.
Stackforce AI infers this person is a SoC Design Verification Engineer with expertise in VLSI and ASIC industries.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 10 mos
Skills
- Design Verification Testing
- System On A Chip (soc)
Career Highlights
- 8+ years in SoC design verification.
- Expertise in low-power verification and coverage closure.
- Proficient in C, SystemVerilog, and UVM methodologies.
Work Experience
AMD
Senior SoC Verification Engineer (Via Mirafra) (7 mos)
Senior SoC Verification Engineer (Via Mirafra) (3 yrs 4 mos)
Mirafra Technologies
Senior Member of Technical Staff (4 yrs 1 mo)
Silicon Works
Component Lead (Via Excelmax) (10 mos)
Excelmax Technologies
Design Verification Engineer (11 mos)
Microchip Technology Inc.
Component Engineer ( Via SkandySys) (3 mos)
Micron Technology
SoC Design Verification Engineer (Via SkandySys) (11 mos)
SkandySys Private Limited
SoC Verification Engineer (1 yr 9 mos)
Education
POST GRADUATE DIPLOMA at National Institute of Electronics and Information Technology (NIELIT) Calicut,India
Spanish Language at Mahatma Gandhi Antarrashtriya Hindi Vishwavidyalaya, Wardha
Bachelor's of Engineering at Bapurao Deshmukh College of Engineering, Sevagram.
