Jitendra Yadav

Software Engineer

Delhi, India6 yrs 4 mos experience

Highly Stable

Key Highlights

Hands-on experience in VLSI design and Verilog programming.
Proven ability to enhance error detection in complex systems.
Developed custom tools for memory design verification.

Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC development and verification.

Contact

Skills

Core Skills

Pcie

Other Skills

LinuxVery-Large-Scale Integration (VLSI)SpecificationsDigital LogicTiming ClosureDigital DesignsRTL CodingCritical ThinkingCircuitLintCDCAXIMicrosoft OfficeCustomer ServiceManagement

About

I am an enthusiast who seeks for new job opportunities and an explorer who always in search of the new type of challenges. I am a postgraduate research student at IIIT Delhi. I am very interested in work related to VLSI design. I have hands-on experience in Verilog and C programming. I had also worked on various tools like a virtuoso, Eldo, RTL Compiler, Vivado HLS, Vivado e.t.c. I had also done some interesting project in Analog Circuit Design.

Experience

6 yrs 4 mos

Total Experience

6 yrs 4 mos

Average Tenure

6 yrs 4 mos

Current Experience

Nvidia

2 roles

Senior asic design engineer

Promoted

Jul 2022 – Present · 3 yrs 10 mos

ASIC Engineer

Jan 2020 – Jun 2022 · 2 yrs 5 mos

Worked in the PCI-E XTL RTL design team.
Responsible for fixing the bugs in the ref manual generation flow script.
Fixing the RTL and testbench due to these changes in the script.
Added logic for enhancing the error detection in the PCI-E XTL side.

LinuxPCIe

Stmicroelectronics

Engineer Intern

Jun 2019 – Dec 2019 · 6 mos · Greater Noida, Uttar Pradesh, India

Worked in the memory design team.
My primary work is focused on to come with the idea for the reduction of test length.
I also worked on a custom fault simulation tool from Synopsys.
We found a bug in the tool during my internship.
I have exposed to address decoder part of the memory for verification of the design to ensure functional safety.

Linux