GOVIND MAURYA

Product Manager

Gurugram, Haryana, India5 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5+ years in PCIe subsystem development
Expertise in PCIe PHY layer and high-speed datapath
Strong proficiency in VHDL and Verilog

Stackforce AI infers this person is a Semiconductor Engineer specializing in PCIe technology and FPGA design.

Contact

Skills

Core Skills

PcieFpga Design

Other Skills

PCIe Gen6VHDLVerilogQuestaSimXilinx VirtexAvery PCIe BFM IPBER analysisVivado ILAInteroperability testingTRUECHIPAVERY BFM IPPCIe Gen5Truechip Gen5 BFM VIPDigital ElectronicsField-Programmable Gate Arrays (FPGA)

About

RTL Design (R & D) Engineer in FPGA department with 5+ years of experience in PCIe Gen5 and Gen6 subsystem development and validation. Deep expertise in PCIe PHY layer, including LTSSM, TX/RX PCS, speed change flows, and high-speed datapath processing. Strong proficiency in VHDL and Verilog, with end-to-end FPGA design and hardware bring-up on Xilinx Virtex platforms. Extensive hands-on experience with PCIe VIPs, interoperability testing with multiple DUTs like AMD, Intel etc. Currently working as a Module Lead, guiding R&D teams and delivering robust, standards-compliant PCIe solutions and parellaly debugging complex rtl issues.

Experience

Logic fruit technologies

3 roles

Module Lead

Promoted

Apr 2023 – Present · 2 yrs 11 mos

@Keysight Loki/Vision – PCIe Gen6
1) Built deep expertise in PCIe PHY behavior, including LTSSM transitions, speed changes, loopback, and high-speed
datapath processing.
2) Modified previously existing RTL modules of PCIe Gen6 LTSSM,TX/RX PCS , compliant with protocol and linktraining requirements.
3) Executed full FPGA design flow on Xilinx Virtex platforms, from synthesis through timing closure and bitstream
generation.
4) Verified functionality of Design using Avery PCIe BFM IP and back-to-back simulations in QuestaSim ensuring
100% protocol compliance.
5) Validated and debugged PCIe links using BER analysis (Keysight M8070B), Vivado ILA, Mark Debug, and simulation-to-silicon correlation.
@ERNIC
1) Analyzed and documented FPGA design blocks, detailing interconnections, functional behavior, and end-to-end data flow to support design understanding and onboarding.
2) Tuned ERNIC IP configuration parameters to achieve targeted throughput and performance objectives on FPGA platforms.
@CREDO
1) Successfully debugged numerous tests for Credo Semiconductors with Avery BFM environment connected back to back with single and double retimers connected in between while using Avery PHY interface.
2) Built custom test cases to verify loopback and compliance functionalities of the Retimer DUT.
3) Gave multiple PCIe protocol demonstrations to the client about topics such as gen6 linkup, data rate change, LTSSM overview, etc.

PCIe Gen6VHDLVerilogFPGA designQuestaSimXilinx Virtex+4

R&D Engineer

Promoted

Apr 2022 – Apr 2023 · 1 yr

@Corvette Exerciser- PCIe Gen6
1) Implemented PCIe Gen6 LTSSM RTL compliant with specifications, supporting B2B and co-simulation flows.
2) Validated PCIe Gen6 PHY using TRUECHIP and AVERY BFM IPs across simulation and hardware platforms.
3) Executed exerciser-based interoperability testing with Intel, AMD, and serial cable DUTs on multiple host systems.
4) Worked across PCIe Gen6 subsystems (LTSSM, TX/RX PCS), debugging and resolving PHY and link-training issues

PCIe Gen6VHDLVerilogInteroperability testingTRUECHIPAVERY BFM IP+2

R&D Engineer Trainee

Aug 2020 – Mar 2022 · 1 yr 7 mos

@Corvette Exerciser- PCIe Gen5
1) Designed and implemented PCIe Gen5 LTSSM RTL using VHDL, enabling seamless Back-to-Back (B2B) and cosimulation verification environments.
2) Validated PCIe Physical Layer (PHY) integrity across simulation and hardware using Truechip Gen5 BFM VIP, ensuring 100% protocol compliance.
3) Executed the validation of Gen5 LTSSM and TX/RX PCS (Physical Coding Sublayer) on Xilinx Virtex FPGA platforms.
4) Performed exerciser-based interoperability testing with Intel, AMD, and serial cable DUTs, with Python-based automation for efficient debug.

PCIe Gen5VHDLVerilogTruechip Gen5 BFM VIPInteroperability testingPCIe+1