Sachin Mathur — DevOps Engineer
16+yrs of experience in full chip integration that involves doing the floorplaning and powerplanning deciding and implementing clocking strategies, physical verification , signal integrity and timing closure , Mask geneartion flow to provide a final and clean gds for tape out. Have worked on Projects for DVD players , STB , Automotive Industry . Have worked on block level place and route, understand and implement clocking structure , do integrity checks , do power and timing analysis for a clean gds for top level integration. Strong knowledge of P&R tools olympus(Mentor), Astro , Magma, physical complier . Worked on 28nm,40nm,55nm , 65nm , 90nm , 0.18um , 0.25um technologies. Have experience of Working on various multisite projects in Europe. Was Involved in Chip timing Closure activity across different modes and corners using olympus(Mentor) for 65nm STB Chip. Involved in Flow Development for CMOS090 project for DVD Recorder from NetlistIn stage to Final GDS .Good command on scripting languages like TCL , perl , scheme , skill. Worked on Custom Layout Design using Virtuoso Layout editor , pre and Post layout simulations using Eldo simulator
Stackforce AI infers this person is a semiconductor design expert with extensive experience in physical design and verification.
Location: Bengaluru, Karnataka, India
Experience: 24 yrs 5 mos
Skills
- Physical Verification
- Place & Route
Career Highlights
- 16+ years in full chip integration.
- Expert in physical design and verification.
- Strong command of P&R tools and technologies.
Work Experience
Intel Corporation
lead physical design engineer (10 yrs 1 mo)
STMICROELECTRONICS
Sr Staff Engineer , Member Techical Staff (2 yrs 8 mos)
Senior Engineering Specialist (2 yrs)
Project Manager (19 yrs 4 mos)
ST Microelectronics Pvt Ltd
Senior Design Engineer (3 yrs 10 mos)
Design Engineer (1 yr 10 mos)
Education
B Tech