Sachin Mathur

DevOps Engineer

Bengaluru, Karnataka, India24 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 16+ years in full chip integration.
  • Expert in physical design and verification.
  • Strong command of P&R tools and technologies.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in physical design and verification.

Contact

Skills

Core Skills

Physical VerificationPlace & Route

Other Skills

TCLStatic Timing AnalysisSignal IntegrityTiming ClosureVLSIASICICSemiconductorsSoCPerlApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)

About

16+yrs of experience in full chip integration that involves doing the floorplaning and powerplanning deciding and implementing clocking strategies, physical verification , signal integrity and timing closure , Mask geneartion flow to provide a final and clean gds for tape out. Have worked on Projects for DVD players , STB , Automotive Industry . Have worked on block level place and route, understand and implement clocking structure , do integrity checks , do power and timing analysis for a clean gds for top level integration. Strong knowledge of P&R tools olympus(Mentor), Astro , Magma, physical complier . Worked on 28nm,40nm,55nm , 65nm , 90nm , 0.18um , 0.25um technologies. Have experience of Working on various multisite projects in Europe. Was Involved in Chip timing Closure activity across different modes and corners using olympus(Mentor) for 65nm STB Chip. Involved in Flow Development for CMOS090 project for DVD Recorder from NetlistIn stage to Final GDS .Good command on scripting languages like TCL , perl , scheme , skill. Worked on Custom Layout Design using Virtuoso Layout editor , pre and Post layout simulations using Eldo simulator

Experience

24 yrs 5 mos
Total Experience
11 yrs 8 mos
Average Tenure
19 yrs 4 mos
Current Experience

Intel corporation

lead physical design engineer

Apr 2016Present · 10 yrs 1 mo · bangalore

TCLStatic Timing AnalysisSignal IntegrityPlace & RouteTiming ClosurePhysical Verification+5

Stmicroelectronics

3 roles

Sr Staff Engineer , Member Techical Staff

Jul 2013Mar 2016 · 2 yrs 8 mos

Senior Engineering Specialist

Jan 2011Jan 2013 · 2 yrs

  • Place and Route Flow from Netlist to GDSII

Project Manager

Jan 2007Present · 19 yrs 4 mos

St microelectronics pvt ltd

2 roles

Senior Design Engineer

Promoted

Oct 2003Aug 2007 · 3 yrs 10 mos

Design Engineer

Nov 2001Sep 2003 · 1 yr 10 mos

Education

B Tech — Electronics & Communication

Jan 1995Jan 1999

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