Sijo P K — Product Engineer

Experienced IP Verification Lead with a strong background in verification methodologies, testbench development, and coverage closure for advanced SoCs and IPs. Proven expertise in leading verification teams, delivering high-quality results, and ensuring robust design validation. Skilled in SystemVerilog, UVM, and end-to-end functional verification. Professional Experience IP Verification Lead | Intel May 2021 – Present Spearheading the verification efforts for 5G and RF IPs, managing a team of skilled verification engineers. Driving the development and execution of Verification Plans, Test Plans, and Functional Coverage Documentation. Architected and implemented SV-UVM Testbenches to support advanced verification environments. Responsible for Functional Verification including test case development and functional coverage bring-up. Developed and implemented SystemVerilog Assertions to enhance verification rigor. Performed regression debugging and achieved 100% regression and code coverage closure, ensuring robust design validation. SoC Verification Engineer | Microchip Technology Jan 2018 – April 2021 Conducted block-level verification of complex SoC components, with a focus on MPU verification. Successfully brought up testbenches, developed SystemVerilog Assertions, and achieved comprehensive coverage goals. Performed regression debugging, ensuring high-quality design verification across multiple projects. Technical Skills Protocol Expertise AXI4, APB, I2C, SPI Programming and Verification Languages Verilog, SystemVerilog (SV), UVM (Universal Verification Methodology) Scripting Perl for automation and productivity in verification environments

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on advanced IP and SoC technologies.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 4 mos