Jesurajvinoth J

Software Engineer

Chennai, Tamil Nadu, India20 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in high-level verification languages like System Verilog and Specman 'e'.
Proficient in developing verification environments from scratch using UVM.
Extensive experience with various protocols including PCIe and USB 3.0.

Stackforce AI infers this person is a Semiconductor Verification Specialist with extensive experience in ASIC and SoC design.

Contact

Skills

Core Skills

Functional VerificationUvmErmAsic VerificationSystem VerilogAsic Design

Other Skills

verificationfunctional correctnesscode coverageSystem CI2CSPIAHBUSB 3.0VerilogASICFPGA & SOC VerificationKnowledge of HVL's like SV & Specman 'e'SoCSpecmanFPGA

About

Expertise in high level verification languages, System verilog & Specman 'e' Experience in developing verification environments from scratch using UVM. Knowledge of AHB, AXI, DDR4, I2C, SPI, PCIe & USB 3.0 Protocols Experience in handling legacy testbenches in both proprietary methodology and standard methodology (viz, eRM, UVM etc...)

Experience

20 yrs 7 mos

Total Experience

2 yrs 6 mos

Average Tenure

8 yrs 7 mos

Current Experience

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Dec 2023 – Present · 2 yrs 5 mos

Staff Engineer

Oct 2017 – Dec 2023 · 6 yrs 2 mos

Pactron inc.

Verification Consultant

Apr 2015 – Oct 2015 · 6 mos · Chennai Area, India

Ericsson

Consultant

Apr 2014 – Jan 2015 · 9 mos · Southampton, United Kingdom

Involved in verification of multiple block level components viz. filters, search core, refinement_search etc... used in video algorithm HEVC using UVM. The environments were build from scratch and functional correctness of the module were verified using standard reference models along with maximum functional & code coverage targets.

UVMverificationfunctional correctnesscode coverageFunctional Verification

Intel corporation

Consultant

Jul 2012 – Dec 2013 · 1 yr 5 mos · Bangalore, India

Involved in block level verification of timers related to mobile application using eRM along with verifying System C model using eRM. I was also involved in block level verification of trace module using UVM.

eRMSystem CUVMFunctional Verification

Infineon technologies

2 roles

Consultant

Oct 2011 – Jul 2012 · 9 mos · Bangalore, India

Role involved verification of a DMA sub-system with multiple proprietary interfaces using eRM.

eRMFunctional Verification

Consultant

Feb 2010 – Apr 2011 · 1 yr 2 mos · Bristol, United Kingdom

Involved in verification of two types of debug module used in automotive application using eRM

eRMFunctional Verification

Test and verification solutions

Project Lead

Oct 2011 – Sep 2017 · 5 yrs 11 mos · Chennai Area, India

L&t infotech

Senior Engineer

Jan 2007 – Sep 2011 · 4 yrs 8 mos · Chennai, India

GDA Tech accquired by L&T Infotech
Involved in verification of I2C, SPI, AHB, WDMA, RDMA of SRIO Subsystem, USB 3.0
Exposure to building environments from scratch in system verilog
Involved in development of all modules of a verification environment.
Exposure to SOC level verification using proprietary existing testbenches.

System VerilogI2CSPIAHBUSB 3.0ASIC Verification

Gda technologies

Engineer

May 2006 – Dec 2006 · 7 mos · Chennai, India

Designed SHA-1, SHA-256, SHA-384, SHA-512 algorithms targeting implementation on Xilinx Virtex-4 device with maximum operating frequency of 90 MHz. The modules were verified using standard reference models in verilog testbench.
I was also involved in design and verification of BISS (Basic Interoperable Scrambling System) IP using verilog.

VerilogASIC Design