Prakhar Bhardwaj

Software Engineer

Bengaluru, Karnataka, India4 yrs 9 mos experience

Highly Stable

Key Highlights

5 years of experience in design verification.
Expert in SystemVerilog and UVM methodologies.
Proven track record in semiconductor industry projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in design verification methodologies.

Contact

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)Risc-vAmba Ahb

Other Skills

MATLABUVMJasperGoldUNIXGITFormal connectivity verificationDPIObject-Oriented Programming (OOP)Very-Large-Scale Integration (VLSI)Digital ElectronicsC (Programming Language)PerlObjectives and Key Results (OKRs)Linux

About

Senior Design Verification engineer at AMD with around 5 years of work experience in verification of IPs, sub systems and SOC with hands on experience in System Verilog, UVM and Perl.

Experience

4 yrs 9 mos

Total Experience

2 yrs 2 mos

Average Tenure

3 mos

Current Experience

Amd

Senior Silicon Design Engineer

Feb 2026 – Present · 3 mos · Bengaluru · Hybrid

SystemVerilogUniversal Verification Methodology (UVM)

Analog devices

Senior Design Verification Engineer

Jan 2025 – Feb 2026 · 1 yr 1 mo · Bengaluru · Hybrid

1. Worked on the functional verification of Tx subsystem involving DSP based MATLAB models and SV-UVM methodology for TB bringup.
2. Worked on the functional verification of RISC-V core based subsystem involving TB bringup, testplan development, coverage analysis and assertion checks.

AMBA AHBRISC-V

Intel corporation

SoC Design Verification Engineer

Aug 2021 – Dec 2024 · 3 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Worked on IP level verification of security IP for server SoCs with focus on feature level verification involving encryption and hashing methodologies.
Worked on SOC level verification of security IP for server SOCs with focus on interface testing such as eSPI.
Worked on formal connectivity verification of security IP using Jasper tool of Cadence.
Have worked on GPIO verification of an ASIC SOC.
Have experience in using tools and software such as System Verilog, UNIX, GVIM, GIT, UVM.
Have worked on defining testplans, tests and verification methodology for block/subsystem and chip-level verification.
Have worked with other verification team disciplines like Emulation and Firmware teams to determine correct functionality.

SystemVerilogUniversal Verification Methodology (UVM)JasperGoldUNIXGIT