Sudhanshu Kumar

Software Engineer

Delhi, India5 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in ASIC design and low power design methodologies.
Hands-on experience with DFT tools and verification processes.
Strong foundation in electronics and VLSI technologies.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in ASIC design and verification.

Contact

Skills

Core Skills

Asic DesignLow Power DesignApplication EngineeringPower IntegrityDesign For TestabilityVerificationSystem VerilogScience EducationCounseling

Other Skills

DFTRTL DesignGenusModusQuesta Advance SimulatorConstraint Random VerificationXilinx VivadoFPGA prototypingMATLABAtmel AVRArduinoATMegaVerilogQuestaSimRTL Verification

About

Being an electronics engineer had always been my interest and that is what I am pursuing. Presently, I am halfway through my B.Tech course. I have an inclination towards the latest electronics technology and VLSI which led me to do a few projects in hardware acceleration of data processing algorithms. I also have training experience in pre-silicon Verification(Functional) and post-silicon Validation(DFT). But at the same time, I also have a keen interest in other non-scholastic aspects of life. Therefore, I can be molded as per the requirements of the employer and will try my best to satisfy the needs of the organisation.

Experience

5 yrs 1 mo

Total Experience

1 yr 8 mos

Average Tenure

4 yrs 7 mos

Current Experience

Nvidia

ASIC Design Engineer

Oct 2021 – Present · 4 yrs 7 mos · Bangalore Urban, Karnataka, India

Low power design team

ASIC DesignLow Power Design

Ansys

2 roles

Application Engineer

Jul 2021 – Oct 2021 · 3 mos · Bengaluru, Karnataka, India

Redhawk-SC

Application Engineering

Intern

Jan 2021 – Jun 2021 · 5 mos · Bengaluru, Karnataka, India

Power Integrity flow development around Redhawk-SC for complex mobile SOC

Power Integrity

Cadence design systems

Trainee

Jun 2020 – Nov 2020 · 5 mos · Noida, Uttar Pradesh, India

Working on projects on adding DFT (Design For Testability) features to various RTL level designs using DFT tools such as Genus and Modus.

Design For Testability

Mentor graphics

Internship Trainee

May 2019 – Jul 2019 · 2 mos · Noida, Uttar Pradesh, India

Training under Mannu K Lauria based on Verification of Electronic Design and Systems using System Verilog. Created a Testing environment for an LC3 RISC microcontroller using System Verilog constructs on Questa Advance Simulator. The design consisted of various layers and modules such as Generator, Driver, Receiver, Scoreboard, Monitor and Interfacing and Clocking blocks. These layers were structured for the purpose of Constraint Random Verification of the faulty DUT design given. Also introduced to basics HLS designing and UVM testing methodology for Testing environments.

VerificationSystem Verilog

Scholr

Science Educator

Jun 2018 – Aug 2018 · 2 mos · Greater Delhi Area

Providing descriptive solutions to the doubts of standard 9-12th of various science subjects on an online platform.

Science Education

Delhi technological university

Co Organizer

May 2018 – Aug 2018 · 3 mos · Greater Delhi Area

Assisted JAC Counselling Team - 2018 during the admission process. Counseled Fresher Students about various opportunities in various engineering branches and handled queries of over 5000 students online as well as in-person.

Counseling