Kuldip Kumar — Software Engineer

Around 12+ years and counting in TEST/DFT !! Working in Nvidia in DFT domain in gate level Scan_insertion and RTL/gate verification. In Synopsys, worked on ATPG tool TetraMax. Handled so far following IPs: • DFTMax Ultra • DFTMax SEQ/XLBIST • DFTMax SEQ+ Has knowledge and experience of followings: • Load/Unload side handling of compression. • Good and fault machine simulation. • Pattern manipulations in DFTMax Ultra. Lately become sought after feature for all customers. • Pattern porting within TetraMax tool. It merges two or more pattern sets together to form a new pattern set at the top, which further can be used in hierarchical ATPG (bottom up flow). • DRC rules • Multi-threading • ATPG engine. Before that worked on ET Checker - A customized DFT Tool, which analyzes RTL/net-list design and checks them for various pre-defined set of DFT rules. It generates various report files with information about design architecture, clock distribution, scan flops, memories, applied constraints, DFT-Rule violations etc. Also worked on RME - RTL Modification Engine. Specialties: TECHNICAL/DFT Languages: C, C++ Scripts: TCL, Perl, Python OS: Linux/Unix, windows Version Control: SVN, CVS, Perforce DOMAIN: DFT, ATPG, TEST Compression, Programming and Debugging, Scripting

Stackforce AI infers this person is a DFT and ATPG specialist in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 16 yrs 8 mos