GIRISH BHARADWAJ .K

CEO

Bengaluru, Karnataka, India15 yrs 3 mos experience
Highly Stable

Key Highlights

  • 11 years of experience in physical design domain.
  • Expertise in full custom layout design and physical verification.
  • Strong background in VLSI design and embedded systems.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in VLSI and physical design.

Contact

Skills

Core Skills

Physical DesignFull Custom Layout Design

Other Skills

Block Level SynthesisSDC developmentLECCLPPnR closureFull chip back end integrationcustom layoutDRCLVSPERCTilingIO ring integrationDDR TimingStatic Power AnalysisVLSI

About

A self-motivated and result oriented focused professional with overall 11 years of experience in physical design domain having worked on XEON Server & Edge Computing products, wireless network-based ASIC/SoC's @ intel Corporation & Freescale Semiconductor, Bangalore. Additionally have work experience of 1 year as lecturer in Dr. mvsit, moodbidri. Completed M.Tech In VLSI Design and Embedded Systems By July 2012. Goal is to work as Physical Design Engineer in Semiconductor Companies. Specialties: Full Custom Layout Design, Physical Design(Synthesis, LEC, PnR, STA), Physical Verification (DRC, LVS, Tiling, XOR, PERC).

Experience

15 yrs 3 mos
Total Experience
3 yrs 5 mos
Average Tenure
2 yrs 4 mos
Current Experience

Amd

SMTS @AMD

Jan 2024Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

SoC Design Engineering Manager

Aug 2016Nov 2024 · 8 yrs 3 mos · bangalore · Hybrid

  • Currently I am working both as Individual contributor and manager at Intel.

Freescale semiconductor

Sr. Design Engineer

Jan 2013Aug 2016 · 3 yrs 7 mos · Bangalore

  • Block Level Synthesis, SDC development, LEC, CLP, PnR closure and Full chip back end integration including custom layout, DRC, LVS, PERC, Tiling, IO ring integration.
Block Level SynthesisSDC developmentLECCLPPnR closureFull chip back end integration+8

Appsconnect technologies pvt ltd

Design Engineer

Sep 2012Dec 2012 · 3 mos · Bangaon, West Bengal, India

  • Physical Design , DDR Timing, Static Power Analysis.
Physical DesignDDR TimingStatic Power Analysis

Intel mobile communications

2 roles

Intern

Jul 2011Jul 2012 · 1 yr

  • COMPLETED ONE YEAR INTERNSHIP IN INTEL MOBILE COMMUNICATIONS, BANGALORE AS PART OF PROJECT WORK FOR M.TECH VLSI DESIGN AT SJCE, MYSORE.

Project#1

Jul 2011Jul 2012 · 1 yr

  • RING OSCILLATOR - FULL CUSTOM MACRO DESIGN

Dr. m. v shetty institute of technology

Lecturer

Sep 2009Aug 2010 · 11 mos · Moodbidri

  • Worked as lecturer in ECE department of Dr. MVSIT, handled Electronic Instrumentation, Linear Integrated Circuits, Basic Electronics and HDL lab.

Education

SJCE, Mysore

M.Tech — VLSI Design & Embedded Systems

Jan 2010Jan 2012

Amrita School of Engineering

B.Tech — Electronics & Communication

Jan 2005Jan 2009

Amrita School of Engineering

B.Tech — Electronics & Communication

Jan 2005Jan 2009

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