Harikrishna Aella

CEO

Hyderabad, Telangana, India14 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC and FPGA design methodologies.
Proven leadership in verification environments.
Strong problem-solving skills in integrated circuits.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and FPGA design.

Contact

Skills

Core Skills

Integrated Circuits (ic)Verification MethodologyLeadership

Other Skills

Problem SolvingNetwork ProtocolsUVMVerification PlanCoverage ClosureLeadership DevelopmentVerilog HDLSystem VerilogCadence IUSMentor Graphics QuestasimSimvisionIMC for coverage analysisXilinx ISE suitePerlWindows

About

Programming Languages: Verilog HDL, System Verilog as HVL EDA Tools: Cadence IUS, Mentor Graphics Questasim, Simvision, IMC for coverage analysis, Xilinx ISE suite Scripting Languages: Perl OS: Windows and Linux Verification Methodology: UVM, OVM Protocols Known: AMBA AXI AHB,APB, I2C SPI, JTAG, UART , QSB Familiar with : Full custom ASIC Design Flow, Semi custom ASIC Design flow and FPGA Design flow

Experience

14 yrs

Total Experience

8 yrs 6 mos

Average Tenure

14 yrs

Current Experience

Amd

Member of Technical Staff

Jan 2022 – Present · 4 yrs 5 mos

Problem SolvingIntegrated Circuits (IC)

Xilinx

Senior Design Verification Engineer

Jan 2018 – Jan 2021 · 3 yrs

Leadership DevelopmentLeadership

Qlogic

ASIC Verification Engineer

Jun 2012 – Present · 14 yrs · Bangalore

Major responsibilities includes owing a block level tesbench, independently work on every verification task from writing verification plan to coverage closure. This also includes Developing the verification components for the given block, and Development of Block level verification environment as per block requirements based on UVM methodology

Network ProtocolsIntegrated Circuits (IC)