Pradnya Patil — Software Engineer
Design Verification Engineer at RTG-SOC IDC, AMD with 5 years of experience in the semiconductor industry. Skilled in Verilog, System Verilog, C++ and have basic level knowledge of perl, Python and UVM. Hands on experience on AMD Instinct MI Projects, have domain knowledge in UCIe protocol, PCIe protocol, Video decoders, hardware virtualization, SR-IOV and hardware interfaces. Tools: Synopsys VCS simulation environment Verdi Waveform Viewer
Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in hardware protocols and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 9 mos
Skills
- Design Verification
- Gate Level Simulation
- Hardware Virtualization
Career Highlights
- 5 years of experience in semiconductor design verification.
- Expertise in UCIe and PCIe protocols.
- Proficient in Verilog and System Verilog.
Work Experience
AMD
Sr. Silicon Design Engineer (2 yrs 5 mos)
Silicon Design Engineer 2 (2 yrs 4 mos)
Co-Op/ Intern (9 mos)
Education
Master of Technology - MTech at Vellore Institute of Technology
Bachelor of Technology - BTech at Dr. Babasaheb Ambedkar Technological University
Diploma at Government Polytechnic, Tasgaon
